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101 Commits

Author SHA1 Message Date
gatecat 0d3a578539 run clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-02-25 11:18:14 +01:00
gatecat 8c6278170b nexus: Support for packing IODELAY and DDR 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-01-26 11:10:53 +01:00
gatecat 94ac6d087e WIP: nexus iodelay 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-01-25 17:00:26 +01:00
gatecat 9ae5de7c7c nexus: Support for CONFIG_LMMI and CONFIG_CLKRST_CORE 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-01-23 09:53:33 +01:00
gatecat ee159126e1 nexus: Support for MULTIBOOT 
Signed-off-by: gatecat <gatecat@ds0.me>
 2026-01-23 09:53:33 +01:00
gatecat 59a29e5f42 nexus: Use a toposort when preplacing clock primitives 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-05-17 06:31:43 +02:00
gatecat 4a4025192a run clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-12-26 09:54:34 +01:00
gatecat 56587859d3 nexus: Improve error reporting for illegal carry chains 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-12-22 15:40:29 +01:00
gatecat fe52840054 archapi: Add new API for global constant routing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-07 09:00:03 +01:00
gatecat a9a9251e42 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-08-31 10:30:19 +02:00
gatecat a01e2c9068 nexus: Be robust to parameters shorter than expected 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-08-23 11:42:39 +02:00
gatecat 61021a22ee nexus: Check IO-bank compatibility 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-02-21 11:18:35 +01:00
gatecat 7845b66512 Add missing <set> includes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-01-20 09:04:41 +01:00
David Lattimore 1602774d27 nexus: Transform registered output parameters 
Dual ported:
OUTREG_A -> OUT_REGMODE_A
OUTREG_B -> OUT_REGMODE_B

Pseudo dual ported:
OUTREG -> OUT_REGMODE_B

Single ported:
OUTREG -> OUT_REGMODE_A
 2022-10-05 14:40:49 +11:00
gatecat c60fb94b6c refactor: Use IdString::in instead of || chains 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-08-10 18:58:22 +01:00
gatecat f7354d092d nexus: Add timing data for LRAM 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-08-10 15:47:22 +01:00
gatecat 77c82b0fbf refactor: id(stringf(...)) to new idf(...) helper 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-08-10 10:57:46 +01:00
gatecat ad502bf64b nexus: Fix CSDECODE parsing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-07-19 09:58:00 +01:00
gatecat 2ed68a21db clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-03-31 10:49:00 +01:00
Maciej Dudek b9e76d1bcd Rename parse_lattice_param to parse_lattice_param_from_cell 
Add new definition for parse_lattice_param

Now parse_lattice_param is design to parse Property rather than search for it in cell.
This functionalty was move to parse_lattice_param_from_cell.

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2022-03-30 14:59:47 +02:00
gatecat 14d53dfec8 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-03-17 19:24:05 +00:00
Maciej Kurc 237391c1b8 nexus: Corrected auto frequency constraint for LF output of OSCA 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-03-16 09:20:15 +01:00
Maciej Kurc 43861c0ee2 nexus: Added support for the DCS Bel 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-03-16 09:20:15 +01:00
gatecat df7e26c1aa clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-03-09 17:12:59 +00:00
Maciej Dudek 191be632e2 nexus: DCCs cannot be cascaded 
This commit solves implicit cascading when clock signal drives DCC and logic

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
 2022-03-09 14:13:29 +01:00
gatecat 86699b42f6 Switch to potentially-sparse net users array 
This uses a new data structure for net.users that allows gaps, so
removing a port from a net is no longer an O(n) operation on the number
of users the net has.

Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-27 13:47:05 +00:00
gatecat 6a32aca4ac refactor: New member functions to replace design_utils 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-18 11:13:18 +00:00
gatecat 76683a1e3c refactor: Use constids instead of id("..") 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-02-16 17:09:54 +00:00
Dan Callaghan 5c30093360 nexus: reduce OSCA worst case to 7% 
The current version of Crosslink-NX Family Data Sheet lists the high
frequency oscillator maximum frequency as 481.5MHz (that is, 7% higher
than its nominal 450MHz):

https://www.latticesemi.com/-/media/LatticeSemi/Documents/DataSheets/CrossLink/FPGA-DS-02049-1-2-1-CrossLink-NX-Family.ashx?document_id=52780

Older documents listed a wider frequency range but ±7% is the range for
production parts.
 2022-02-10 15:48:06 +11:00
Maciej Kurc 3042f9e792 Fixed correction of Nexus OSCA frequency constraints 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-02-02 09:24:28 +01:00
Maciej Kurc e51e82d6a9 Added honoring OSCA output frequency tolerance during constraints generation 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-01-28 13:51:10 +01:00
Maciej Kurc 18f71ace8c Removed the need for MULT36_CORE bel for implementing the MULTADDSUB9X9WIDE macro 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2022-01-25 12:08:52 +01:00
gatecat 35feb7ebba clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-12-12 13:02:39 +00:00
Maciej Kurc 41accf84ce Added checking if all FFs added to an existing cluster have matching configuration 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-11-23 15:16:26 +01:00
Maciej Kurc 238da79e52 Fixed potential issues with carry-chain cluster expansion, added a parameter controlling the ratio of FFs that got glued to carry-chain clusters. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-11-22 13:13:28 +01:00
Maciej Kurc 5bc97c94ae Added appending FFs to other existing LUT cluster types (carry, widefn) 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-11-22 10:23:24 +01:00
Maciej Kurc 086bcf0615 Added an option to control LUT and FF packing 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-11-22 10:23:24 +01:00
Maciej Kurc d97f93ee88 Added clustering free LUTs and FFs 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-11-22 10:23:24 +01:00
gatecat 53e94653f3 nexus: Fix DSP macro placement 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-09-22 13:12:21 +01:00
Maciej Kurc 80e2f8a791 Added support for syn_useioff for enabling tri-state control FF integration into IOLOGIC. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-20 11:35:36 +02:00
Maciej Kurc 8ffd30cb2d Use correct names for IDDRX1_ODDRX1 FASM features 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-17 15:52:56 +02:00
Maciej Kurc ef9eee6b15 Added automatic inference and integration of FFs driving T pin into IOLOGIC 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-17 13:49:35 +02:00
Maciej Kurc 6948d41616 Added handling of the case when tri-state control net bypasses SIOLOGIC bel 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2021-09-17 13:49:35 +02:00
gatecat 5686fdcf1c nexus: Basic packer and FASM support for I/ODDR 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-07-28 13:27:02 +01:00
gatecat 2ffb081442 Fixing old emails and names in copyrights 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-12 13:22:38 +01:00
gatecat ecc19c2c08 Using hashlib in arches 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 15:05:19 +01:00
gatecat 579b98c596 Use hashlib for core netlist structures 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-06-02 14:27:56 +01:00
gatecat c6fa1a179a nexus: Use new cluster API 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-06 12:25:32 +01:00
gatecat 08c7f97b1e nexus: Support for hard DPHY 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-08 15:59:18 +00:00
gatecat 7922b3bfc4 Replace DelayInfo with DelayPair/DelayQuad 
This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.

This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.

While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.

Signed-off-by: gatecat <gatecat@ds0.me>
 2021-02-19 11:31:33 +00:00