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2,718 Commits 30 Branches 9 Tags 21 MiB
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201 Commits

Author SHA1 Message Date
Miodrag Milanovic 7a95629aff Fix clangformat and execute it 2020-06-27 13:20:16 +02:00
whitequark 89e0cc8078 Simplify and improve chipdb embedding/loading. 2020-06-26 08:36:07 +00:00
whitequark 1dc1164dce CMake: rewrite chipdb handling from ground up. 2020-06-25 14:03:37 +00:00
whitequark e7bb04769d Port nextpnr-{ice40,ecp5} to WASI. 
This involves very few changes, all typical to WASM ports:
  * WASM doesn't currently support threads or atomics so those are
    disabled.
  * WASM doesn't currently support exceptions so the exception
    machinery is stubbed out.
  * WASM doesn't (and can't) have mmap(), so an emulation library is
    used. That library currently doesn't support MAP_SHARED flags,
    so MAP_PRIVATE is used instead.

There is also an update to bring ECP5 bbasm CMake rules to parity
with iCE40 ones, since although it is possible to embed chipdb into
nextpnr on WASM, a 200 MB WASM file has very few practical uses.

The README is not updated and there is no included toolchain file
because at the moment it's not possible to build nextpnr with
upstream boost and wasi-libc. Boost requires a patch (merged, will
be available in boost 1.74.0), wasi-libc requires a few unmerged
patches.
 2020-05-23 20:57:26 +00:00
David Shah 84327b634c ecp5: MULT18X18D timing fixes 
Signed-off-by: David Shah <dave@ds0.me>
 2020-05-01 08:17:29 +01:00
Ross Schlaikjer a1160068c8
No cell delay for clocked MULT18X18D 2020-04-30 11:09:22 -04:00
Ross Schlaikjer 0043ae0807
Issue warning for mixed-mode inputs 2020-04-29 14:39:52 -04:00
Ross Schlaikjer 6625284950
Handle register timing case 2020-04-29 13:58:52 -04:00
Ross Schlaikjer a4fa953740
Use registered port class on mult18x18 2020-04-29 11:08:53 -04:00
Ross Schlaikjer 5e763b1afc
Alter MULT18X18D timing db based on register config 
If the REG_INPUTA_CLK and REG_INPUTB_CLK values are set, then we should
use the faster setup/hold timings for the 18x8 multiplier.
Similarly, check the value of REG_OUTPUT_CLK for whether or not to use
faster timings for the output.

This is based on how I currently understand the registers to work - if
anyone knows the actual rules for when each timing applies please do
chime in to correct this implementation if necessary.

Along the same lines, this PR does not address the case when the
pipeline registers are enabled, since it is not clear to me how exactly
that affects the timing.
 2020-04-28 20:01:29 -04:00
David Shah 396dfb7d5e
Merge pull request #423 from rschlaikjer/rschlaikjer-regmode-timing-database 
Add support for REGMODE to DP16KD
 2020-04-07 20:02:29 +01:00
Ross Schlaikjer 3257bdc8a1
Actually just move all the logic to ArchInfo 2020-04-07 14:11:49 -04:00
Ross Schlaikjer 0bdf1e05f1
Extract regmode configuration to ArchInfo 2020-04-07 14:03:55 -04:00
Ross Schlaikjer c007463168
Change timing database lookup based on REGMODE value 2020-04-07 13:48:21 -04:00
David Shah 3b49c20f43 ecp5: Proper support for '12k' device 
Signed-off-by: David Shah <dave@ds0.me>
 2020-03-13 11:22:11 +00:00
David Shah 2248e07b66 router2: Improve flow and log output 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-03 13:46:05 +00:00
David Shah 7123209324 Allow selection of router algorithm 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-03 11:54:38 +00:00
David Shah ad1cc12df1 router2: Make magic numbers configurable 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-03 11:38:31 +00:00
David Shah 5e1aac67db ecp5: Improve bounding box accuracy 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-03 11:38:31 +00:00
David Shah d2c77fd9ae ecp5: router2 main rename 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-03 11:38:31 +00:00
David Shah abdaa9c8a1 ecp5: Router2 test integration 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-03 11:38:30 +00:00
Miodrag Milanovic 796d648995 Merge remote-tracking branch 'origin/master' into mmicko/ecp5_gui 2019-12-28 13:54:06 +01:00
Miodrag Milanovic 436260e47e move bel creation to gfx.cc 2019-12-15 09:21:58 +01:00
Miodrag Milanovic fb27f1a031 fix formating 2019-12-14 16:40:27 +01:00
Miodrag Milanovic ebbfb6375d more new wires added 2019-12-14 09:18:24 +01:00
Miodrag Milanovic 19eb16045f ebr, mult and alu nice display 2019-12-14 08:21:02 +01:00
Miodrag Milanovic 7fd856b866 clangformat run 2019-12-08 09:33:06 +01:00
Miodrag Milanovic 275805d78f display IOs properly 2019-12-07 19:06:10 +01:00
Miodrag Milanovic 401bee6111 More bels show properly 2019-12-07 18:52:33 +01:00
Miodrag Milanovic 76d2a3f0db add dcca bels and dummy parts for other bels 2019-12-07 17:41:22 +01:00
Miodrag Milanovic 74f2c4a73b more pips, and valid mapping 2019-11-10 15:24:06 +01:00
Miodrag Milanovic f6d74cb7a9 Draw some pips, fixed H6 and V6 2019-11-09 13:12:20 +01:00
David Shah 475fcd4425 ecp5: Add an error for out-of-sync constids and bba 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-26 20:38:28 +01:00
David Shah 36c07a0f45 ecp5: Fix routing to shared DSP control inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-25 09:37:13 +01:00
Miodrag Milanovic 49760a9ea8 Show V02/V06/H02/H06 2019-10-25 09:28:08 +02:00
Miodrag Milanovic 0d2ae5cc9d Split graphics calls for wires into gfx.cc 2019-10-20 11:12:26 +02:00
Miodrag Milanovic e9ae0cf7ce muxes only together with slices 2019-10-20 09:41:48 +02:00
Miodrag Milanovic eaf760768b Remove not used line 2019-10-20 09:41:48 +02:00
Miodrag Milanovic e69bb4c077 Simplify layout of elements 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 3b01d2fbce fix slice wire 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 399a137a77 bound signals 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 8c79044d43 more wires between switchboxes 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 4cbdc388b8 Add more types of wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 966d0dec19 finixed slice wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 74da9cc424 wd wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 4b79050ef4 Fix look of some wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic a59faa8df0 Add output wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 07a8022a1f fix mux display 2019-10-20 09:41:48 +02:00
Miodrag Milanovic a11cc8791b set wire active flag 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 3da7af9f02 clk and lsr muxes 2019-10-20 09:41:48 +02:00