23 Commits

Author	SHA1	Message	Date
Eddie Hung	75654a69f0	Fix LUT input delays, speedup construct_wire_to_delay?	2018-11-11 14:15:11 -08:00
Eddie Hung	83117bef66	Add missing APIs needed for router_improve	2018-11-11 10:19:17 -08:00
Eddie Hung	5c56fab0ab	[xc7] Add torc_info->site_index_to_bel lookup; also fix Arch::getBelByName()	2018-11-03 15:56:06 -07:00
Eddie Hung	aa7f7d6a97	clangformat	2018-11-03 15:18:26 -07:00
Eddie Hung	db6e81d6c3	Populate Arch::getWireDelay()	2018-09-04 10:11:10 -07:00
Eddie Hung	d78f5a1d5b	Build a pip_to_dst_wire lookup to speedup routing	2018-09-03 22:59:34 -07:00
Eddie Hung	3a5665c1cb	Speedup placement slightly using bel_to_loc	2018-09-03 21:00:11 -07:00
Eddie Hung	d2597bcd8d	Fix segments	2018-09-03 00:10:16 -07:00
Eddie Hung	7e693ff27d	Precompute pips too	2018-09-02 19:06:20 -07:00
Eddie Hung	ca7eef26ac	Wires now encapsulate segments	2018-09-02 16:57:11 -07:00
Eddie Hung	a7ccc01c45	Use getBelType()	2018-08-19 17:38:55 -07:00
Eddie Hung	17918b5992	Fix for multiple id_SLICE_LUT6 per actual SLICE	2018-08-17 23:05:12 -07:00
Eddie Hung	b8b9813056	id_QUARTER_SLICE -> id_SLICE_LUT6, fix getBelLocation()	2018-08-14 08:42:27 -07:00
Eddie Hung	72c785db0e	Convert to use torc_info	2018-08-12 22:09:16 -07:00
Eddie Hung	56b7299cca	{SLICEL,SLICEM} -> QUARTER_SLICE	2018-08-12 20:21:03 -07:00
Eddie Hung	f6f20dce0c	Rename ddb to torc	2018-08-12 19:20:13 -07:00
Eddie Hung	57c273898c	Finishes placement now	2018-08-11 22:24:13 -07:00
Eddie Hung	2bc7ffc2ea	WIP	2018-08-11 21:13:49 -07:00
Eddie Hung	8cddc49abc	Starts placement onto all Xilinx sites	2018-08-11 18:52:48 -07:00
Eddie Hung	45009ac09d	Remove timing, remove wires	2018-08-11 17:08:50 -07:00
Eddie Hung	8357417787	Load Torc DDB	2018-08-11 15:53:55 -07:00
Eddie Hung	6425032ec4	Rip out ice40 stuff, put xc7z020 in	2018-08-11 15:00:31 -07:00
Eddie Hung	d53658a079	Copy ice40 into xc7	2018-08-11 14:35:49 -07:00