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4842 Commits

Author SHA1 Message Date
Lofty d557e3e35f hashlib: constify const_iterators 2024-01-04 17:32:56 +01:00
Lofty 2c8ad5fa1d Fix a renamed Qt item 2024-01-04 17:32:56 +01:00
Lofty d867019dcb upgrade to C++17 2024-01-04 17:32:56 +01:00
gatecat 5013392841 Add trivially copyable invariant for ID types 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-01-04 17:04:28 +01:00
dragonmux 6a9ad61051 rust: Fixed an unused parameter warning 2024-01-04 10:39:45 +01:00
dragonmux cb269b46d6 rust: Made the wrap helper `inline` and fixed an accidental copy error 2024-01-04 10:39:45 +01:00
dragonmux 3e46fbc655 rust: Reworked the unwrap helpers by effectively hiding the crime of memcpy()'ing into a non-POD type from the compiler 
There is still the possibility that this can explode horribly, but the result should be the same codegen and fixes the warning

This also makes the helpers `inline` so they'll usually be compiled out for a nice speed boost
 2024-01-04 10:39:45 +01:00
dragonmux cfeb588d32 rust: Reworked `npnr_context_get_pips_leak()` using std::accumulate() and fixed an accidental copy problem 2024-01-04 10:39:45 +01:00
dragonmux 7d0c4eaf1b rust: Reworked `npnr_context_get_wires_leak()` using std::accumulate() and fixed an accidental copy problem 2024-01-04 10:39:45 +01:00
dragonmux e9c69ac00c gui: Fixed unused parameters and spurious `;` warnings in one of the headers 2024-01-04 10:39:45 +01:00
dragonmux cb4db2d368 ice40: Fixed unused parameters and spurious `;` warnings in some of the headers 2024-01-04 10:39:45 +01:00
dragonmux 7fd80c5a92 common/kernel: Fixed unused parameters and spurious `;` warnings in some of the headers 2024-01-04 10:39:45 +01:00
Lofty 50d43742ce rust: silence warnings 2024-01-03 14:51:33 +01:00
gatecat e12ab86c75 rust: Fix segfault 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-01-03 13:42:18 +01:00
Lofty 1bbcc5f2c4 (broken) third round of review fixes 2024-01-03 13:42:18 +01:00
Lofty 49d505831d second round of review fixes 2024-01-03 13:42:18 +01:00
Lofty 1dbd81067a first round of review fixes 2024-01-03 13:42:18 +01:00
Lofty d2297b1ba0 Add Rust FFI bindings 2024-01-03 13:42:18 +01:00
gatecat 4a4025192a run clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-12-26 09:54:34 +01:00
Miodrag Milanovic 41914876ef .gitignore for nextpnr-himbaechel 2023-12-23 11:09:26 +01:00
gatecat 56587859d3 nexus: Improve error reporting for illegal carry chains 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-12-22 15:40:29 +01:00
gatecat 535709a9a9 placer1: Fix various bitrot 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-12-13 11:37:30 +01:00
Lofty d1083fd348 static/ice40: bug fixes for ultraplus 2023-12-13 11:37:20 +01:00
Miodrag Milanovic b4ca68c8ef Add ability to override Cluster methods in Himbaechel 2023-12-11 13:53:52 +01:00
gatecat 6d9322457e static: Reduce stddev of initial solution 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-26 16:51:47 +01:00
YRabbit c13b34f20e gowin: Himbaechel. Add BSRAM for all chips. 
The following primitives are implemented for the GW1N-1, GW2A-18,
    GW2AR-18C, GW1NSR-4C, GW1NR-9C, GW1NR-9 and GW1N-4 chips:

    * pROM     - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
    * pROMX9   - read only memory - (bitwidth: 9, 18, 36).
    * SDPB     - semidual port    - (bitwidth: 1, 2, 4, 8, 16, 32).
    * SDPX9B   - semidual port    - (bitwidth: 9, 18, 36).
    * DPB      - dual port        - (bitwidth: 16).
    * DPX9B    - dual port        - (bitwidth: 18).
    * SP       - single port      - (bitwidth: 1, 2, 4, 8, 16, 32).
    * SPX9     - single port      - (bitwidth: 9, 18, 36).

    For GW1NSR-4C and GW1NR-9 chips, SP/SPX9 primitives with data widths
    of 32/36 bits are implemented using a pair of 16-bit wide
    primitives.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-11-26 13:08:09 +01:00
YRabbit 90d4863dd4 gowin: Himbaechel. Add GW1NZ-1 BSRAM. 
The following primitives are implemented for the GW1NZ-1 chip:

* pROM     - read only memory - (bitwidth: 1, 2, 4, 8, 16, 32).
* pROMX9   - read only memory - (bitwidth: 9, 18, 36).
* SDPB     - semidual port    - (bitwidth: 1, 2, 4, 8, 16, 32).
* SDPX9B   - semidual port    - (bitwidth: 9, 18, 36).
* DPB      - dual port        - (bitwidth: 16).
* DPX9B    - dual port        - (bitwidth: 18).
* SP       - single port      - (bitwidth: 1, 2, 4, 8, 16, 32).
* SPX9     - single port      - (bitwidth: 9, 18, 36).

Also:
 - The creation of databases for GW1NS-2 has been removed - this was not
   planned to be supported in Himbaechel from the very beginning and
   even examples were not created in apicula for this chip due to the
   lack of boards with it on sale.
 - It is temporarily prohibited to connect DFFs and LUTs into clusters
   because for some reason this prevents the creation of images on lower
   chips (placer cannot find the placement), although without these
   clusters the images are quite working. Requires further research.
 - Added creation of ALU with mode 0 - addition. Such an element is not
   generated by Yosys, but it is a favorite vendor element and its
   support here greatly simplifies the compilation of vendor netlists.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-11-26 13:08:09 +01:00
YRabbit f2c280feda gowin: Himbaechel. Initial BSRAM support 
Only pROM/pROMX9 for now

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-11-26 13:08:09 +01:00
Miodrag Milanovic e3f4578b3b CRLF -> LF eol 2023-11-23 09:22:07 +01:00
Miodrag Milanovic ec60542ffd create wiremap for himbaechel arch 2023-11-23 09:22:07 +01:00
Miodrag Milanovic 1ec8e411d7 set render bound box, so grid is displayed 2023-11-23 08:21:26 +01:00
Miodrag Milanovic 0b8a93eed5 fix compile warning 2023-11-23 08:21:26 +01:00
gatecat de3d5be8f0 python: Remove deprecated use of Py_SetProgramName 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-23 06:49:15 +01:00
Balint Cristian 7814f44883 Fix abstract class implementation for fpga_interchange 
Signed-off-by: Balint Cristian <cristian.balint@gmail.com>
 2023-11-23 06:49:01 +01:00
gatecat 6683fd4ada himbaechel: Fix when more then 32k unique node shapes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-22 17:11:27 +01:00
gatecat 55635cf2cd Update README 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-17 09:14:19 +01:00
gatecat e2a887ef0d himbaechel: Switch default back to router1 for now 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-17 09:09:59 +01:00
gatecat 5bfe0dd1b1 himbaechel: Adding a xilinx uarch for xc7 with prjxray 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-14 17:12:09 +01:00
laanwj a32ad13a86 ecp5: Don't segfault while packing FFs when DI port of TRELLIS_FF unconnected 
Currently a segfault happens when the DI port is not specified. Leaving
it unconnected is probably incorrect, but it shouldn't crash the placer.
Fix by adding a check.
 2023-11-14 11:55:51 +01:00
uis a4d2244300 Fix printf formats 2023-11-13 13:59:51 +01:00
YRabbit 0106c3d299 gowin: Himbaechel. Diff io BUGFIX. 
Fixed incorrect use of attributes instead of parameters.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2023-11-13 13:59:28 +01:00
Lofty 506d5f9422 machxo2: less pessimistic delay prediction 2023-11-09 06:48:50 +01:00
gatecat 4c6003ac0b router2: Don't use estimates for constant nets 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-07 15:55:22 +01:00
gatecat 7b0e082000 clangformat 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-07 09:02:35 +01:00
gatecat cf647463e4 himbaechel: Add support for new constants API 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-07 09:00:03 +01:00
gatecat fe52840054 archapi: Add new API for global constant routing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-11-07 09:00:03 +01:00
Lofty e3c44dd20a ice40: add IO group to static 2023-11-07 08:18:35 +01:00
Lofty 214cc4315e static: density multiplier should be a vector 2023-11-07 08:18:35 +01:00
Lofty d6f54fd9df ice40: add static placer support 2023-10-29 08:46:33 +01:00
gatecat d40c6e850d himbaechel: Generation speedup and improvements 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-10-29 07:46:45 +01:00