377f56c151
interchange: Cope with undriven nets in more places
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-14 10:58:42 +01:00
2ffb081442
Fixing old emails and names in copyrights
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-12 13:22:38 +01:00
b65dbd5c9e
interchange: clusters: always get cell bel map and add asserts
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-06-11 11:19:01 +02:00
64b45848d7
interchange: run clang formatter
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-06-11 11:19:01 +02:00
d72c10cb6c
interchange: clusters: adjust comments
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-06-11 11:19:01 +02:00
e8191dc061
interchange: increase chipinfo version
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-06-11 11:19:01 +02:00
490ca794c5
interchange: tests: counter: emit carries for xc7
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-06-11 11:19:01 +02:00
104536b7aa
interchange: add support for generating BEL clusters
...
Clustering greatly helps the placer to identify and pack together
specific cells at the same site (e.g. LUT+FF), or cells that are chained through
dedicated interconnections (e.g. CARRY CHAINS)
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-06-11 11:19:01 +02:00
3cc58b3918
fpga_interchange: Add site router tests
...
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2021-06-11 08:43:30 +01:00
dcbb322447
Remove redundant code after hashlib move
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:20 +01:00
eca1a4cee4
Use hashlib in most remaining code
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:20 +01:00
ecc19c2c08
Using hashlib in arches
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:19 +01:00
579b98c596
Use hashlib for core netlist structures
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 14:27:56 +01:00
ff72454f83
Add hash() member functions
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 14:27:56 +01:00
0426ba4e87
interchange: Add LIFCL-40 EVN tests
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-01 09:52:40 +01:00
bae83857a3
interchange: Add macro parameter mapping
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-21 10:00:35 +01:00
64f5b1d031
interchange: Don't error out on missing cell ports
...
This is required for LUTRAM support, as the upper address bits of
RAMD64E etc are missing for shallower primitives.
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-21 10:00:35 +01:00
a146dbdb03
interchange: Add LUTRAM test
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-21 10:00:35 +01:00
2759480cb5
interchange: Preliminary implementation of macro expansion
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-21 10:00:35 +01:00
237b27e50b
interchange: Add macro param map rules to chipdb
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-21 10:00:35 +01:00
012b60c9ca
interchange: Add macro data to chipdb
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-21 10:00:35 +01:00
84359f39c5
interchange: phys: add site instance idstr for pseudo tile PIPs
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-05-19 18:48:54 +02:00
5a41d2070c
Run clangformat
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-16 16:25:05 +01:00
428b56570d
interchange: pseudo pips: fix illegal tile pseudo PIPs
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-05-14 12:17:53 +02:00
8c468acff8
interchange: site router: add valid pips list to check during routing
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-05-13 11:00:42 +02:00
fd93697a2d
interchange: arch: do not allow site pips within sites
...
During general routing, the only site pips that can be allowed are those
which connect a site wire to the routing interface.
This might be too restrictive when dealing with architectures that
require more than one site PIPs to route from a driver within a site to the routing
interface (which is something that should be allowed in the
interchange).
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-05-12 18:28:22 +02:00
7a1a95a2d6
interchange: Fix bounding box computation
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-11 13:02:23 +01:00
45618faf36
interchange: site router: fix log messages
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-05-10 14:20:54 +02:00
beff2b912c
interchange: site router: fix illegal site thru paths
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-05-10 14:05:46 +02:00
9a1cad85fe
interchange: Adding a basic global buffer placer
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-07 10:28:59 +01:00
9b3fb00908
interchange: Initial global routing implementation
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-07 10:28:56 +01:00
b8c8200683
interchange: Add more global cell info
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-07 10:25:18 +01:00
0d6be6f474
Add stub cluster API impl for remaining arches
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-06 13:12:52 +01:00
49caad0b7b
interchange/nexus: Add counter example
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-30 14:15:37 +01:00
dcb09ec8de
interchange: Implement getWireType
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-30 11:07:31 +01:00
ecf24201ec
interchange: Add wire types to chipdb
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-30 11:07:14 +01:00
3fd1ee7757
Merge pull request #683 from antmicro/interchange-allow-loc-keyword
...
interchange: allow LOC keyword in XDC files
2021-04-20 14:12:14 +01:00
d1548ed317
interchange: allow LOC keyword in XDC files
...
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
2021-04-20 14:35:15 +02:00
18459a9e4c
interchange: Handle disconnected/missing cell pins
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-19 10:46:35 +01:00
872b3aa63d
interchange: Add default cell connections to chipdb
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-19 10:16:26 +01:00
d4aac6586c
Add Python bindings for placement tests
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-15 10:00:45 +01:00
8f5185c381
Merge pull request #678 from acomodi/initial-fasm-generation
...
interchange: add FASM generation target and clean-up tests
2021-04-14 14:28:01 +01:00
dfc9c3df8c
interchange: add FASM generation target and clean-up tests
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-04-14 14:36:07 +02:00
4e346ecfba
Hash table refactoring
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-14 10:30:19 +01:00
06e54f08e6
interchange: Allow pseudo-cells with no input pins
...
These are used for the LUT-as-GND-driver pseudo-pips in the Nexus arch,
which will probably be required for UltraScale too.
Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-13 10:58:41 +01:00
fc15105643
clangformat
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-12 10:26:39 +01:00
93e34b8754
interchange: Disambiguate cell and bel pins when creating Vcc ties
...
The pins created for tieing to Vcc were being named after the bel pin,
relying on the fact that Xilinx names cell and bel pins differently for
LUTs. This isn't true for Nexus devices which uses the same names for
both, and was causing a failure as a result.
This uses a "PHYS_" prefix that's highly unlikely to appear in a cell
pin name to disambiguate.
Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-09 10:26:32 +01:00
ae2f7551c1
[interchange] Provide estimateDelay when USE_LOOKAHEAD is not defined.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-04-06 10:42:05 -07:00
3200026e1f
[interchange] Remove requirement to have wire_lut.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-04-06 10:42:05 -07:00
c2a6f6ce62
[interchange] Fix invalid use of local variables due to refactoring.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-04-06 10:42:05 -07:00
gatecat
Alessandro Comodi
Tomasz Michalak
Jan Kowalewski
Keith Rothman