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nextpnr
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3,768 Commits 33 Branches 9 Tags 27 MiB
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3768 Commits

Author SHA1 Message Date
gatecat 34677d3883 mistral: Workaround for weird SCLR issue 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 9221acc9e2 mistral: Fix ENA and ACLR bitstream generation 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 4d32c4f2fc mistral: Disable global buffers that are currently broken 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 511e46c40f router2: Reduce verbosity when debugging 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat e1aaf715c6 mistral: Compensate for EF_SEL mirroring in validity check 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 87ebada258 mistral: Fix EF_SEL and BTO_DIS 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 8bc9732d49 mistral: PKREG bits appear to be mirrored within a half? 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 757a10c247 mistral: Debugging flipflops 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat dce847b2f3 mistral: Trim SDATA if SLOAD is low 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat b29fa1d24c mistral: FF&CLKBUF fixes, part 1 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 66b3a192f8 mistral: First pass at FF and CLKBUF bitgen 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat b2f45b1aab mistral: Account for TD input count limit 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat bd525d3548 msitral: Fix pip iterator Python bindings 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 8c7fa8e6c9 mistral: Implement PIP locations, too 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 6ad329c540 mistral: Implement bounding boxes for router2 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat e688ee0e89 mistral: Debugging carry chain issues 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 3313d5267a mistral: Adding FF control set reservation 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 09a867310b mistral: Carry fixes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 3d1bb4f1b2 mistral: Carry debugging 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 2f2fde7e6c mistral: Write arith mode to bitstream (not yet functional) 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat d39e67da7e mistral: First pass at carry packing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 7574eab2b6 mistral: FF validity checking fixes 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 18e05ec852 mistral: Fix constant trimming 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat bacba274a2 mistral: Write LUT inits 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat d1f635242d mistral: Add some IO configuration 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat dea4c6f53f mistral: Setting some more boilerplate bits 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 27eb3be7da mistral: Add stub RBF generation 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat ad5e5f80ca mistral: Rename clock buffer primitive 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat a581526528 mistral: Python and GUI stub 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 386b5b901c mistral: Implement some misc. things 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat c5d983066d mistral: Some preps for generating bitstreams 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 2612853238 mistral: Adding a function for computing ALM LUT masks 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 5d191f8297 mistral: Add IO packing 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 96f16c8635 mistral: Add a basic QSF parser 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 595b354184 mistral: Add some packing logic based on nexus 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 3fc5396063 mistral: Working on FF validity checking 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 1b729d90d0 mistral: Add the 'pin style' stuff based on Nexus 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat d38ff14264 mistral: Working on ALM input assignment 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat e5e2f7bc62 mistral: Add stub pack/place/route functions 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 879ac39e53 mistral: Renamed arch from cyclonev 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 2938682295 cyclonev: Rebase update 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 9eb0bc482e cyclonev: More validity checking thoughts 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat a6ea72fd84 cyclonev: Add validity check and IO bels 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat fbdcfa9c42 cyclonev: First (untested) pass at ALM validity checking 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 1cd22b81da cyclonev: More preparations for validity checking 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 9bd7ef5f5f cyclonev: Preparations for validity checking 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 24af19b58d cyclonev: Fix some archcheck fails 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 431c4cec9f cyclonev: Rework bels 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat 86ce6abf6a cyclonev: Outline LAB structure 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00
gatecat c671961c18 cyclonev: Outline functions for creating bels/wires/pips 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-05-15 14:54:33 +01:00