The GW-5A series has 8 flip-flops in a cell instead of 6. These
additional flip-flops can be used if the control network matches that
for the 4th and 5th DFFs in this cell.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Prior to the 5A series, pin functions (GPIO/SSPI/JTAG/DONE/etc) were
switched using fuses. This was done during the binary image formation
stage for loading into the FPGA using the command line keys of the
gowin_pack program.
The 5A series features certain ports that connect to VCC or GND
depending on whether the pin is used as SSPI or GPIO, for example. This
mechanism exists in parallel with fuses, but it is not described
anywhere, nor is there a corresponding primitive.
To generate working images, we have no choice but to simulate this thing
at the nextpnr stage, since VCC/GND routing is required.
For now, two flags are added, responsible for the SSPI and I2C pin
functions.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Preparing to support the 5A series.
Family recognition is added, as well as minor fixes, but base generation
itself is not allowed for GW5 - this gives the ability to test the next
Apicula release and still not break installations for those who simply
specify `HIMBAECHEL_GOWIN_DEVICES = "all"`.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Recognize GW5A family chips.
Construct chip base name for
- GW5A-LV25MG121C1/l0 - TangPrimer 25k
- GW5AT-LV60PG484A - TangMega 60k
- GW5AST-LV138PG484A - TangMega 138k
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
---------
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Add log output
* Optimize CC_LUT1
* Update tests
* Optimize CC_LUT2 as well
* Use init enumerations
* Merge DFF in MX4
* Move repack code
* Move ramio code to pack_cpe
* Merge LUT1/2 to ADDF inputs
* Note actual CPE ports
* Merge DFF in ADDF
* Update FF params and ports first
* Check if DFFs are compatible before merging
* Optimize DFF/Latch
* Add reporting of optimized cells
* Optimize MX2/4
* Add statistics
* Use special nets for VCC/GND to skip using name
* Add warning for carry chain split
* Merge FFs where possible
* Cleanup
* Keep statistics out for now
* Add logs for packing sections
* review fixes
---------
Co-authored-by: Lofty <dan.ravensloft@gmail.com>
Adds automatic connection of a general-purpose pin to the global clock
network.
The old behaviour, where such networks have to be explicitly specified,
can be activated with the command line key
"--vopt disable_gp_clock_routing".
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* CPE mapping improvements
* Use CP_OUT for adders
* Fixes
* Small fixes
* Cleanups
* Cleanup
* Cleanups
* Fixes
* Fixes
* Optimize
* Cleanup
* clangformat
* Cleanup
* Cleanup
* Bump required version of database
* Cleanup
* Resolve name conflicts
* Fix signal routing
* Make CPE_LATCH separate
* Add more timings models, need updated values
* Fixed warning
* multiplier support from lofty/gatemate-mult
* explicitly zero some params in B passthrough
* comment the relevant CPE inputs in check_multipliers
* Rename some of bels
* remove _lower from name
* refactor multiplier checking
* Revert "remove _lower from name"
This reverts commit daa1041bdf.
* Fixe net name to be unique
* Make sure we at least generate bitstream with all info
* Simplify zero
* Bounded cell type in gui
* typo fix
* Remove A passthrough inversion option
* Clean up CarryGenCell config
* Update a passthru to use new primitives
* Cleanup for adders
* Clean up MsbRoutingCell
* Cleanup
* Refactor A connection code
* Make it more as in PR #1513
* Added cplines to bpassthru and fixed constant driver for A
* Add parts
* Added comp out connections
* clangformat
* clangformat
* Clean up B passthrough connections
* wire up a bunch of intermediate signals
* Bit of cleanup
* handing of C_EN_IN
* C_EN_CIN fixes
* connect f_route to its lines
* fix cite for FRoutingCell
* fixup, oops
* connect multfab to its lines
* Commented line
* Connect CPOUTs
* Handle C_I params
* connect CINY1 for CarryGenCell
* fix carry gen CINX
* Update L2T4 model
* Updates for ADDCIN
* clangformat
* fix some issues with multfab and f_route
* look at C_I when doing inversion
* Only set some C_I signals when used
* Fix one more place
* do not use cplines so we can merge in one cell
* Cover cases that could be optimized out
* clangformat
* Cleanups
* Disable multiplier usage for now
---------
Co-authored-by: Lofty <dan.ravensloft@gmail.com>
YRabbit
Miodrag Milanović
Lofty
José Miguel Sánchez García