Commit Graph

563 Commits

Author SHA1 Message Date
Nathaniel Graff 08f68518f2 Fix spelling of 'unsupported'
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2020-05-13 20:00:37 -07:00
David Shah 84327b634c ecp5: MULT18X18D timing fixes
Signed-off-by: David Shah <dave@ds0.me>
2020-05-01 08:17:29 +01:00
Ross Schlaikjer a1160068c8
No cell delay for clocked MULT18X18D 2020-04-30 11:09:22 -04:00
Ross Schlaikjer de6ddc470b
Further condense 2020-04-29 14:52:29 -04:00
Ross Schlaikjer 6e8082860e
Dedupe clock error check 2020-04-29 14:46:09 -04:00
Ross Schlaikjer 0043ae0807
Issue warning for mixed-mode inputs 2020-04-29 14:39:52 -04:00
Ross Schlaikjer 6625284950
Handle register timing case 2020-04-29 13:58:52 -04:00
Ross Schlaikjer a4fa953740
Use registered port class on mult18x18 2020-04-29 11:08:53 -04:00
Ross Schlaikjer 5e763b1afc
Alter MULT18X18D timing db based on register config
If the REG_INPUTA_CLK and REG_INPUTB_CLK values are set, then we should
use the faster setup/hold timings for the 18x8 multiplier.
Similarly, check the value of REG_OUTPUT_CLK for whether or not to use
faster timings for the output.

This is based on how I currently understand the registers to work - if
anyone knows the actual rules for when each timing applies please do
chime in to correct this implementation if necessary.

Along the same lines, this PR does not address the case when the
pipeline registers are enabled, since it is not clear to me how exactly
that affects the timing.
2020-04-28 20:01:29 -04:00
David Shah de00c00aac ecp5: Fix CSDECODE bitgen
Signed-off-by: David Shah <dave@ds0.me>
2020-04-15 20:25:56 +01:00
David Shah 64d3e3e1e8 ecp5: Use dedicated routing for ECLKs where possible
Signed-off-by: David Shah <dave@ds0.me>
2020-04-14 19:20:13 +01:00
Miodrag Milanovic 96c14abd1f Add TRELLIS_PROGRAM_PREFIX 2020-04-11 22:05:30 +02:00
David Shah a8111bba83 ecp5: Fix routing bitgen for non-SERDES 'VCIB' tiles
Signed-off-by: David Shah <dave@ds0.me>
2020-04-10 08:25:16 +01:00
David Shah ced336492c ecp5: Make hysteresis default-on for LVCMOS33 bidir as well as input
Signed-off-by: David Shah <dave@ds0.me>
2020-04-09 21:36:27 +01:00
David Shah 396dfb7d5e
Merge pull request #423 from rschlaikjer/rschlaikjer-regmode-timing-database
Add support for REGMODE to DP16KD
2020-04-07 20:02:29 +01:00
Ross Schlaikjer 3aecb3b08c
No need to fetch context 2020-04-07 14:44:19 -04:00
Ross Schlaikjer fc591421f9
Change assert to error 2020-04-07 14:42:27 -04:00
Ross Schlaikjer e46b990251
Rearrange bool algebra 2020-04-07 14:31:17 -04:00
Ross Schlaikjer 3257bdc8a1
Actually just move all the logic to ArchInfo 2020-04-07 14:11:49 -04:00
Ross Schlaikjer 0bdf1e05f1
Extract regmode configuration to ArchInfo 2020-04-07 14:03:55 -04:00
Ross Schlaikjer c007463168
Change timing database lookup based on REGMODE value 2020-04-07 13:48:21 -04:00
David Shah e8933f8519
Merge pull request #419 from garytwong/handle-opendrain
Handle OPENDRAIN attribute.
2020-04-07 09:44:40 +01:00
Gary Wong ec1eea9990 Fix assertion failure on invalid LOCATE input.
Trying to parse this invalid LPF syntax:

    LOCATE COMP "a" SITE "A1"
    IOBUF PORT "a" IO_TYPE=LVCMOS33;

(note missing semicolon on first line) gives an assertion failure in
strip_quotes, because the fifth token is scanned as "A1"IOBUF (without
a trailing quote).

Avoid the problem by detecting extraneous input and issuing a more
specific error.
2020-04-05 21:42:45 -06:00
Gary Wong 31e9fffadd Handle OPENDRAIN attribute. 2020-04-03 17:59:19 -06:00
David Shah f9a76c56f7 ecp5: Allow use of IDDRXN and ODDRXN type primitives on the same pin
Signed-off-by: David Shah <dave@ds0.me>
2020-04-03 09:53:14 +01:00
Gary Wong 8cc6a2fae5 Remove comment about the USRMCLK primitive being untested.
Tested and verified working: the trivial configuration:

    module USRMCLK( USRMCLKI, USRMCLKTS );
        input USRMCLKI, USRMCLKTS;
    endmodule

    module top( input clk );
        reg[ 24:0 ] count = 0;

        always @( posedge clk ) begin
            count <= count + 1'b1;
        end

        USRMCLK mspi( .USRMCLKI( count[ 20 ] ), .USRMCLKTS( count[ 24 ] ) );
    endmodule

produces the expected output (toggling at high frequency, toggling
tri-state at lower frequency) on an LFE5U-85 when fed with an appropriate
clock.  See https://bayimg.com/AAnNKAAGO for an example.  The top
(magenta) trace is the MCLK line.
2020-04-02 21:35:35 -06:00
Martin 707289c8d6 Enum/int compatibility for EHXPLLL parameters
- Lattice component EHXPLLL parameter compatibility, allowing to
  pass an int parameter for the enum (as expected by trellis tile)
  e.g. CLKOP_TRIM_DELAY : integer := 0;
2020-04-02 14:25:00 +02:00
David Shah 3b49c20f43 ecp5: Proper support for '12k' device
Signed-off-by: David Shah <dave@ds0.me>
2020-03-13 11:22:11 +00:00
David Shah bb73580209
Merge pull request #400 from YosysHQ/dave/tri-fixes
Improve handling of unused inout port bits
2020-03-10 13:50:59 +00:00
David Shah 751f4556fd ecp5: Fix differential inputs
Signed-off-by: David Shah <dave@ds0.me>
2020-03-08 11:32:34 +00:00
Sylvain Munaut 054be6fb67 build: Default the ECP5 and iCE40 roots to the install prefix
If the user specifies a custom install prefix, chances are icestrom/trellis
are also in that prefix rather than the hardcoded /usr/local

Fixes #351

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2020-03-03 15:32:10 +01:00
David Shah 9aa22433ff Improve handling of unused inout port bits
Signed-off-by: David Shah <dave@ds0.me>
2020-02-25 14:26:47 +00:00
Sebastian Birke 2c938e0e8b Rename cmake path variable TRELLIS_ROOT to TRELLIS_INSTALL_PREFIX 2020-02-04 18:19:45 +01:00
Jared Boone 1b560ae44c CMake: Changing the definition of TRELLIS_ROOT to point to root of lib, share containing trellis libs and data
two other commit message of squashed commits:
CMake: Search for user lib inside trellis instead of libtrellis

CMake: Fix missing path component for share contents
2020-02-04 18:19:45 +01:00
David Shah 1ceffbe0bc
Merge pull request #391 from YosysHQ/router2-upstream
Upstreaming router2
2020-02-04 16:08:08 +00:00
David Shah b4d029a55c
Merge pull request #385 from YosysHQ/router1-arc-fixes
Fixes for partial reconfig demo
2020-02-03 13:55:07 +00:00
David Shah 2248e07b66 router2: Improve flow and log output
Signed-off-by: David Shah <dave@ds0.me>
2020-02-03 13:46:05 +00:00
David Shah 7123209324 Allow selection of router algorithm
Signed-off-by: David Shah <dave@ds0.me>
2020-02-03 11:54:38 +00:00
David Shah ad1cc12df1 router2: Make magic numbers configurable
Signed-off-by: David Shah <dave@ds0.me>
2020-02-03 11:38:31 +00:00
David Shah 5e1aac67db ecp5: Improve bounding box accuracy
Signed-off-by: David Shah <dave@ds0.me>
2020-02-03 11:38:31 +00:00
David Shah d2c77fd9ae ecp5: router2 main rename
Signed-off-by: David Shah <dave@ds0.me>
2020-02-03 11:38:31 +00:00
David Shah abdaa9c8a1 ecp5: Router2 test integration
Signed-off-by: David Shah <dave@ds0.me>
2020-02-03 11:38:30 +00:00
Erika 9185c85a54 python: Expose PlaceStrength enum and isValidBelForCell on ecp5
Signed-off-by: Erika <rrika9@yahoo.com>
2020-01-26 20:32:02 +00:00
David Shah 3b5e64e8c6 ecp5: Fix tieoff of unused DELAY signals
Signed-off-by: David Shah <dave@ds0.me>
2020-01-21 19:02:26 +00:00
David Shah 7c81d4e630 ecp5: Add SPICB0 IO support
Signed-off-by: David Shah <dave@ds0.me>
2020-01-20 20:30:14 +00:00
David Shah 9dc8e1e35d ecp5: Don't reroute existing globals
Signed-off-by: David Shah <dave@ds0.me>
2020-01-20 14:58:38 +00:00
Miodrag Milanovic 714769e1b8 Few more caught by clang 2020-01-18 15:58:09 +01:00
David Shah 54c1bc1538
Merge pull request #382 from YosysHQ/ecp5-psuedodiff
ecp5: Add support for top pseudo diff outputs
2020-01-16 09:38:00 +00:00
David Shah f513d5fff4 ecp5: Add support for top pseudo diff outputs
Signed-off-by: David Shah <dave@ds0.me>
2020-01-15 11:43:12 +00:00
Larry Doolittle eba6ea53f8 More adjustments to .bba file locations
Follows PM discussion with Marcus Comstedt.
Extend changes in .bba file location (made in commit b6a7b60) to ice40 and MSVC cases,
  so all cases become compatible with read-only access to git tree.
Only known down-side is inefficiency when building out-of-tree for multiple architectures;
  people following that use case should consider using PREGENERATED_BBA_PATH.
It would be nice if there were less copy-paste in MSVC vs. non-MSVC content in family.cmake,
  but that would have to be addressed by someone more skilled in Cmake and MSVC.
2020-01-14 12:28:40 -08:00