* gowin: add DL-series latch cell support
Teach the himbaechel Gowin backend to recognize and place all 12
DL-series latch primitives onto DFF BEL sites. Latches use the CLK
pin for the gate signal and share placement resources with DFFs.
* gowin: convert latches to DFFs with LATCH attribute during packing
Instead of teaching all DFF infrastructure about 12 DL latch types,
pack_latches() converts them to corresponding DFF types early and sets
a LATCH attribute. This attribute is picked up by gowin_pack to set
REGMODE=LATCH instead of FF.
* gowin: exclude latch gate signals from clock buffer promotion
Latch cells are mapped to DFFs with a LATCH attribute, so their gate
signal drives the CLK port. This caused pack_buffered_nets to promote
the gate signal onto a global clock buffer (BUFG), which has different
timing/initialization behavior and caused the first gate transition
to be lost. Skip CLK pins on cells with the LATCH attribute when
checking for clock users.
* gowin: update latch message to be user friendly.
Dual Port has a defective output register. This only manifests itself at
small data widths and only on -C chips.
That is, Tangprimer20k (GW2A-18) works perfectly, while Tangnano20k
(GW2A-18C) stutters. The same story with GW1N-9 and GW1N-9C.
Fortunately, the fix has long been included in nextpnr for SDP memory,
so all that remains is to call the same function for Dual Port.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
- Added support for ALU running in "2" ADDSUB mode, the mode that yosys generates for gowin;
- Supports specifying an arbitrary input carry as well as passing the output carry to logic;
- A small restructuring of the source files.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Justin
YRabbit