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Author SHA1 Message Date
Gary Wong 8cc6a2fae5 Remove comment about the USRMCLK primitive being untested. 
Tested and verified working: the trivial configuration:

    module USRMCLK( USRMCLKI, USRMCLKTS );
        input USRMCLKI, USRMCLKTS;
    endmodule

    module top( input clk );
        reg[ 24:0 ] count = 0;

        always @( posedge clk ) begin
            count <= count + 1'b1;
        end

        USRMCLK mspi( .USRMCLKI( count[ 20 ] ), .USRMCLKTS( count[ 24 ] ) );
    endmodule

produces the expected output (toggling at high frequency, toggling
tri-state at lower frequency) on an LFE5U-85 when fed with an appropriate
clock.  See https://bayimg.com/AAnNKAAGO for an example.  The top
(magenta) trace is the MCLK line.
 2020-04-02 21:35:35 -06:00
Martin 707289c8d6 Enum/int compatibility for EHXPLLL parameters 
- Lattice component EHXPLLL parameter compatibility, allowing to
  pass an int parameter for the enum (as expected by trellis tile)
  e.g. CLKOP_TRIM_DELAY : integer := 0;
 2020-04-02 14:25:00 +02:00
David Shah 3b49c20f43 ecp5: Proper support for '12k' device 
Signed-off-by: David Shah <dave@ds0.me>
 2020-03-13 11:22:11 +00:00
David Shah bb73580209
Merge pull request #400 from YosysHQ/dave/tri-fixes 
Improve handling of unused inout port bits
 2020-03-10 13:50:59 +00:00
David Shah 751f4556fd ecp5: Fix differential inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2020-03-08 11:32:34 +00:00
Sylvain Munaut 054be6fb67 build: Default the ECP5 and iCE40 roots to the install prefix 
If the user specifies a custom install prefix, chances are icestrom/trellis
are also in that prefix rather than the hardcoded /usr/local

Fixes #351

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2020-03-03 15:32:10 +01:00
David Shah 9aa22433ff Improve handling of unused inout port bits 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-25 14:26:47 +00:00
Sebastian Birke 2c938e0e8b Rename cmake path variable TRELLIS_ROOT to TRELLIS_INSTALL_PREFIX 2020-02-04 18:19:45 +01:00
Jared Boone 1b560ae44c CMake: Changing the definition of TRELLIS_ROOT to point to root of lib, share containing trellis libs and data 
two other commit message of squashed commits:
CMake: Search for user lib inside trellis instead of libtrellis

CMake: Fix missing path component for share contents
 2020-02-04 18:19:45 +01:00
David Shah 1ceffbe0bc
Merge pull request #391 from YosysHQ/router2-upstream 
Upstreaming router2
 2020-02-04 16:08:08 +00:00
David Shah b4d029a55c
Merge pull request #385 from YosysHQ/router1-arc-fixes 
Fixes for partial reconfig demo
 2020-02-03 13:55:07 +00:00
David Shah 2248e07b66 router2: Improve flow and log output 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-03 13:46:05 +00:00
David Shah 7123209324 Allow selection of router algorithm 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-03 11:54:38 +00:00
David Shah ad1cc12df1 router2: Make magic numbers configurable 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-03 11:38:31 +00:00
David Shah 5e1aac67db ecp5: Improve bounding box accuracy 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-03 11:38:31 +00:00
David Shah d2c77fd9ae ecp5: router2 main rename 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-03 11:38:31 +00:00
David Shah abdaa9c8a1 ecp5: Router2 test integration 
Signed-off-by: David Shah <dave@ds0.me>
 2020-02-03 11:38:30 +00:00
Erika 9185c85a54 python: Expose PlaceStrength enum and isValidBelForCell on ecp5 
Signed-off-by: Erika <rrika9@yahoo.com>
 2020-01-26 20:32:02 +00:00
David Shah 3b5e64e8c6 ecp5: Fix tieoff of unused DELAY signals 
Signed-off-by: David Shah <dave@ds0.me>
 2020-01-21 19:02:26 +00:00
David Shah 7c81d4e630 ecp5: Add SPICB0 IO support 
Signed-off-by: David Shah <dave@ds0.me>
 2020-01-20 20:30:14 +00:00
David Shah 9dc8e1e35d ecp5: Don't reroute existing globals 
Signed-off-by: David Shah <dave@ds0.me>
 2020-01-20 14:58:38 +00:00
Miodrag Milanovic 714769e1b8 Few more caught by clang 2020-01-18 15:58:09 +01:00
David Shah 54c1bc1538
Merge pull request #382 from YosysHQ/ecp5-psuedodiff 
ecp5: Add support for top pseudo diff outputs
 2020-01-16 09:38:00 +00:00
David Shah f513d5fff4 ecp5: Add support for top pseudo diff outputs 
Signed-off-by: David Shah <dave@ds0.me>
 2020-01-15 11:43:12 +00:00
Larry Doolittle eba6ea53f8 More adjustments to .bba file locations 
Follows PM discussion with Marcus Comstedt.
Extend changes in .bba file location (made in commit b6a7b60) to ice40 and MSVC cases,
  so all cases become compatible with read-only access to git tree.
Only known down-side is inefficiency when building out-of-tree for multiple architectures;
  people following that use case should consider using PREGENERATED_BBA_PATH.
It would be nice if there were less copy-paste in MSVC vs. non-MSVC content in family.cmake,
  but that would have to be addressed by someone more skilled in Cmake and MSVC.
 2020-01-14 12:28:40 -08:00
Larry Doolittle b6a7b607fd Remove barrier to out-of-tree builds 
With this change, nextpnr can build successfully (and run correctly) using the git tree as a read-only reference.
No change in behavior observed for in-tree builds.
 2020-01-12 21:11:56 -08:00
Miodrag Milanovic fb5480cde3 clangformat 2019-12-28 15:02:13 +01:00
Miodrag Milanovic 59f4755e8f made most of frequent numbers constants 2019-12-28 15:01:36 +01:00
Miodrag Milanovic 6cca93543b move constants to gfx.cc 2019-12-28 14:27:14 +01:00
Miodrag Milanovic 6ebe2fd034 remove synt example 2019-12-28 14:08:58 +01:00
Miodrag Milanovic 796d648995 Merge remote-tracking branch 'origin/master' into mmicko/ecp5_gui 2019-12-28 13:54:06 +01:00
Miodrag Milanovic 50f87a6024 add newline at eof 2019-12-28 13:51:02 +01:00
David Shah 0d43aff268 ecp5: Always promote IOLOGIC SCLK to global 
Fixes #374

Signed-off-by: David Shah <dave@ds0.me>
 2019-12-27 15:53:00 +00:00
David Shah fe40094216 Preserve hierarchy through packing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-27 10:44:30 +00:00
David Shah b100087024 python: Add bindings for hierarchy structures 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-27 10:44:30 +00:00
David Shah b6e2159cec Work around Qt MOC issue with IdString enums 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-27 10:32:23 +00:00
Miodrag Milanovic a05954249a optimize and set order 2019-12-20 14:02:00 +01:00
Miodrag Milanovic c26c5e7b8e clang format 2019-12-20 09:07:03 +01:00
Miodrag Milanovic e4210e7fd3 Add all missing wires 2019-12-20 09:05:58 +01:00
Miodrag Milanovic b271e59472 Add global wires 2019-12-15 17:20:48 +01:00
Miodrag Milanovic d5174110fa more pips on connection box 2019-12-15 10:57:24 +01:00
Miodrag Milanovic f2b8e347a9 cleanup and formating 2019-12-15 10:43:30 +01:00
Miodrag Milanovic 2872b500e3 make it more simetric 2019-12-15 10:33:12 +01:00
Miodrag Milanovic bbc05f3113 optimize and add some missing pips 2019-12-15 10:07:55 +01:00
Miodrag Milanovic 3d42097e9d cleanup 2019-12-15 09:45:09 +01:00
Miodrag Milanovic fa55a826b2 cleanup wire 2019-12-15 09:26:25 +01:00
Miodrag Milanovic 436260e47e move bel creation to gfx.cc 2019-12-15 09:21:58 +01:00
Miodrag Milanovic fb27f1a031 fix formating 2019-12-14 16:40:27 +01:00
Miodrag Milanovic cce27e72f0 lot more pips 2019-12-14 16:29:25 +01:00
Miodrag Milanovic abf9bc3bb9 fixes and more pips 2019-12-14 16:10:41 +01:00
Miodrag Milanovic d42ecc081e pips for alu, mult and memory 2019-12-14 13:00:09 +01:00
Miodrag Milanovic 7e7e20742d pips for ios 2019-12-14 12:30:04 +01:00
Miodrag Milanovic 601360b73a propagate w and h 2019-12-14 10:56:26 +01:00
Miodrag Milanovic e118e418e5 pips for other type of connection box 2019-12-14 09:39:41 +01:00
Miodrag Milanovic ebbfb6375d more new wires added 2019-12-14 09:18:24 +01:00
Miodrag Milanovic 19eb16045f ebr, mult and alu nice display 2019-12-14 08:21:02 +01:00
Miodrag Milanovic 6d005f38b5 add more 2019-12-13 19:44:49 +01:00
Miodrag Milanovic 2a5f0bbd28 new wires in db 2019-12-13 18:24:49 +01:00
Miodrag Milanovic c0585e98eb added siologic 2019-12-13 14:32:27 +01:00
Miodrag Milanovic 16f6aaa68c Add many new wires 2019-12-13 14:01:28 +01:00
Miodrag Milanovic 7fd856b866 clangformat run 2019-12-08 09:33:06 +01:00
Miodrag Milanovic 275805d78f display IOs properly 2019-12-07 19:06:10 +01:00
Miodrag Milanovic 401bee6111 More bels show properly 2019-12-07 18:52:33 +01:00
Miodrag Milanovic 76d2a3f0db add dcca bels and dummy parts for other bels 2019-12-07 17:41:22 +01:00
Miodrag Milanovic b764f9b13a Fix edge wires 2019-12-07 17:21:59 +01:00
David Shah 349be76d26 ecp5: Add support for flipflops with preload 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-07 12:20:25 +00:00
Miodrag Milanovic 0c77eed07d add more pips 2019-12-01 11:00:24 +01:00
David Shah 1c1c096861 ecp5: Fix 25k DDRDLLA bitstream gen 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-29 10:56:04 +00:00
David Shah ff30bc87fe ecp5: Fix placement of DDRDLLA 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-29 10:50:13 +00:00
David Shah b4e9f5c3a6
Merge pull request #356 from YosysHQ/ecp5-ff-density 
ecp5: Improve flipflop packing density
 2019-11-27 11:22:14 +00:00
David Shah 98fe4438f1 ECP5 support is no longer experimental 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-26 16:10:53 +00:00
David Shah aee2e01983 ecp5: Improve flipflop packing density 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-20 18:22:22 +00:00
David Shah 08cf545d9b Revert "Merge pull request #355 from YosysHQ/ecp5-promote-lsr" 
This reverts commit 6a7d1fe53d, reversing
changes made to c3d4117a21.
 2019-11-20 17:10:11 +00:00
David Shah 67e216f8fb ecp5: Add support for promotion of LSRs to global network 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-19 14:08:35 +00:00
David Shah c3d4117a21 ecp5: Fix handling of custom DEL_VALUE 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-18 22:03:11 +00:00
David Shah 36c0ff2dbc ecp5: Fix dynamic DELAYF control 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-18 20:58:08 +00:00
David Shah 9a848d9d76 ecp5: Add logic utilisation before packing statistics 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-18 16:54:42 +00:00
David Shah d08e2ade88
Merge pull request #345 from YosysHQ/dave/sdf 
Improve handling of top level IO and add SDF support
 2019-11-18 14:28:40 +00:00
Miodrag Milanovic da8b5758cd Handle H00 and V00 2019-11-11 13:30:11 +01:00
Miodrag Milanovic 2827731210 More pips and fix for V01 2019-11-11 12:49:26 +01:00
Miodrag Milanovic 522bbbc1f2 cleanup 2019-11-11 09:32:28 +01:00
Miodrag Milanovic 6e349db55b proper h06 and v06 2019-11-11 08:58:46 +01:00
Miodrag Milanovic afea345cc7 More pips added 2019-11-10 17:02:18 +01:00
Miodrag Milanovic 74f2c4a73b more pips, and valid mapping 2019-11-10 15:24:06 +01:00
Miodrag Milanovic 43c7b4fa21 Fixed V2, some more pips 2019-11-10 11:10:13 +01:00
Miodrag Milanovic 9a9265f4d2 more pips 2019-11-10 10:08:02 +01:00
Miodrag Milanovic f6d74cb7a9 Draw some pips, fixed H6 and V6 2019-11-09 13:12:20 +01:00
David Shah 21c09c8b8f ecp5: Copy timing constraints across ECLKBRIDGECS 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-01 16:27:51 +00:00
David Shah 58b7cb920f ecp5: Fix placement of ECLKBRIDGECS 
Signed-off-by: David Shah <dave@ds0.me>
 2019-11-01 16:07:51 +00:00
David Shah 5cf0ed5ede ecp5: Allow setting drive strength for 3V3 IOs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-26 22:21:18 +01:00
David Shah bac8335222 ecp5: Add constids for new timing cell types 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-26 20:50:50 +01:00
David Shah 475fcd4425 ecp5: Add an error for out-of-sync constids and bba 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-26 20:38:28 +01:00
David Shah 36c07a0f45 ecp5: Fix routing to shared DSP control inputs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-25 09:37:13 +01:00
Miodrag Milanovic 49760a9ea8 Show V02/V06/H02/H06 2019-10-25 09:28:08 +02:00
Miodrag Milanovic d1feb2aa2d display horizontal wires, add some globals to list 2019-10-23 18:17:08 +02:00
David Shah b582ba810c ecp5: Make database build depend on constids.inc 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-20 10:29:07 +01:00
Miodrag Milanovic 0d2ae5cc9d Split graphics calls for wires into gfx.cc 2019-10-20 11:12:26 +02:00
Miodrag Milanovic 847910d986 type needs to be part of hash for GroupId 2019-10-20 10:03:37 +02:00
Miodrag Milanovic e9ae0cf7ce muxes only together with slices 2019-10-20 09:41:48 +02:00
Miodrag Milanovic eaf760768b Remove not used line 2019-10-20 09:41:48 +02:00
Miodrag Milanovic e69bb4c077 Simplify layout of elements 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 3b01d2fbce fix slice wire 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 399a137a77 bound signals 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 8c79044d43 more wires between switchboxes 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 4cbdc388b8 Add more types of wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 28d0313ccc Less types needed 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 966d0dec19 finixed slice wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 74da9cc424 wd wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 4b79050ef4 Fix look of some wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic a59faa8df0 Add output wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 07a8022a1f fix mux display 2019-10-20 09:41:48 +02:00
Miodrag Milanovic a11cc8791b set wire active flag 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 3da7af9f02 clk and lsr muxes 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 0b4ced96ec draw rest of slice wires and more from switchbox 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 3e117ce792 Optimize 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 49b12a828a Add other side of slice wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic 1ae64d7bf5 Display rest of slice input wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic f7a6d4dc06 Start adding visible wires 2019-10-20 09:41:48 +02:00
Miodrag Milanovic eafc0e4e9e Added type to wire 2019-10-20 09:41:48 +02:00
Miodrag Milanovic bfbb6dbf69 Draw swbox, smaller slices, proper io 2019-10-20 09:41:30 +02:00
David Shah a22f86f861 ice40: Preserve top level IO properly 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-19 13:01:00 +01:00
David Shah cf5cbd1153 ecp5: Preserve top level IO properly 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-18 15:58:57 +01:00
David Shah 8f86ccc412 ecp5: Add support for ECLKBRIDGECS 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-11 14:52:31 +01:00
David Shah f2fd1bf80a ecp5: Fix tristate IO registers 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-09 14:35:16 +01:00
David Shah c6401413a4 ecp5: Add support for IO registers 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-09 14:23:35 +01:00
David Shah a14555c8d1 ecp5: Add IDDR71B support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-09 12:07:56 +01:00
David Shah 21847a55e0 ecp5: Add ODDR71B support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-09 11:23:20 +01:00
David Shah 9b83e67460 ecp5: Preparations for new IO bels 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-09 10:55:10 +01:00
David Shah cba36239a4 ecp5: Fix parameters 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-04 14:54:31 +01:00
David Shah d04e5954a6 ecp5: Adding support for 36-bit wide PDP RAMs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-01 12:01:33 +01:00
David Shah cb71b488ec
Merge pull request #332 from YosysHQ/dave/python-refactor 
Improving Python API and adding docs for it
 2019-09-19 20:15:42 +01:00
David Shah 8351ae275e Merge branch 'precompiled-bba' of https://github.com/xobs/nextpnr into xobs-precompiled-bba 2019-09-19 16:02:10 +01:00
David Shah f8719a5717
Merge pull request #330 from zeldin/bba 
bba: Default to native endian in bbasm
 2019-09-19 15:57:23 +01:00
Sean Cross 062091e9e4 ecp5: add support for PREGENERATED_BBA_PATH 
Support pre-generated bba files to speed up compiling on Windows
and get it compiling on Darwin.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-17 11:32:44 +08:00
David Shah d5e4986e1b python: Refactor out bindings shared between ECP5 and iCE40 
Signed-off-by: David Shah <dave@ds0.me>
 2019-09-15 16:15:07 +01:00
David Shah c2299c8972 python: Fix getWireBelPins 
Fixes #327

Signed-off-by: David Shah <dave@ds0.me>
 2019-09-15 15:59:16 +01:00
Marcus Comstedt 2f9b04fd56 CMake: Generate chipdbs in build tree when building out-of-tree 
Signed-off-by: Marcus Comstedt <marcus@mc.pp.se>
 2019-09-15 13:42:17 +02:00
Marcus Comstedt 3d9ce8836c bba: Require explicit endianness flag, and supply it 
Signed-off-by: Marcus Comstedt <marcus@mc.pp.se>
 2019-09-15 12:30:03 +02:00
David Shah bc6b47efe0
Merge pull request #329 from YosysHQ/dave/net_aliases 
json: Add support for net aliases
 2019-09-13 19:01:26 +01:00
David Shah 95540763b9 json: Add support for net aliases 
Signed-off-by: David Shah <dave@ds0.me>
 2019-09-13 17:27:15 +01:00
David Shah 2ace9b5ad3 ecp5: Move clock constraints across IO and DCCA 
Signed-off-by: David Shah <dave@ds0.me>
 2019-09-13 16:50:07 +01:00
Sean Cross f98960b936 ecp5: use $PYTHON_EXECUTABLE for python path 
Sometimes the python executable might have a different name.  Cmake
sets the $PYTHON_EXECUTABLE variable to point to the binary path,
so use this variable.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-09 22:10:51 +08:00
David Shah 04be9a71f9 ecp5: Add support for clock gating with DCCA 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-31 10:45:12 +01:00
David Shah 9f9920f92b ecp5: Add full part name to bitstream header 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-27 14:36:20 +01:00
David Shah 78f86ce67a ecp5: Add GSR/SGSR support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-27 13:14:41 +01:00
Arnaud Durand a26c9bb6d9 Rename clock restriction attribute to "noglobal" 2019-08-24 18:09:42 +02:00
Arnaud Durand a947f09bfb Restrict clock promotion to global 2019-08-22 00:43:03 +02:00
David Shah c70f87e4c5
Merge pull request #309 from YosysHQ/dsptiming 
ecp5: Conservative analysis of comb DSP timing
 2019-08-09 10:27:15 +01:00
David Shah c9969c1593 Add deprecation warning for default packages 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 21:35:55 +01:00
David Shah f0abbc71b5 ecp5: Fix handling of missing ports in LUT permutation 
Fixes #310

Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 21:24:01 +01:00
David Shah e55946bec7 clangfromat 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-07 14:46:53 +01:00
David Shah 661237eb64 ecp5: Add --out-of-context for building hard macros 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-07 14:22:47 +01:00
David Shah 7126dacccd ecp5: Add a check for legacy parameter values 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-06 09:53:33 +01:00
David Shah ec48f8f464 ecp5: New Property interface 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-05 17:22:37 +01:00
David Shah 1839a3a770 Major Property improvements for common and iCE40 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-05 14:52:15 +01:00
David Shah d297a96dc1 ecp5: Fix missing LUT inputs, fixes #301 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-10 09:34:22 +01:00
David Shah 2da41a66c7 ecp5: Conservative analysis of comb DSP timing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-08 15:09:54 +01:00
David Shah 8f2813279c
Merge pull request #284 from YosysHQ/json_write 
Initial support for writing to json files from nextpnr.
 2019-07-03 12:39:38 +01:00
whitequark 1b3c8ea9c1 CMake: serialize chipdb generation by default. 
Fixes #296.
 2019-06-26 21:31:24 +00:00
whitequark 640285755e CMake: formatting. NFC. 2019-06-26 21:27:57 +00:00
Miodrag Milanovic be47fc3e9a clangformat run 2019-06-25 18:19:25 +02:00
Miodrag Milanovic ec47ce2320 Merge master 2019-06-25 18:14:51 +02:00
Miodrag Milanovic 9affcf82d9 default for 5G is speed 8 2019-06-21 18:06:01 +02:00
David Shah df8688c227 ecp5: Delay tweaking for lower speed grades 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-21 10:55:23 +01:00
David Shah 7ae64b9477 ecp5: Reduce cfg.criticalityExponent for now 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-21 10:20:46 +01:00
Miodrag Milanovic 66ea9f39f7 enable lading of jsons and setting up context 2019-06-14 15:18:35 +02:00
Miodrag Milanovic 36ccc22fc9 Use flags for each step 2019-06-14 09:59:04 +02:00
Miodrag Milanovic ca7e944d7a restore arch info for ecp5 2019-06-14 08:55:11 +02:00
Miodrag Milanovic 03dff10cbd Load properties from json and propagate to context create 2019-06-13 20:42:11 +02:00
Miodrag Milanovic 4de147d9e4 Save settings that we saved in project 2019-06-13 18:39:16 +02:00
Miodrag Milanovic 1cd4a4d17a Remove concept of project and code connected 2019-06-13 17:42:41 +02:00
Miodrag Milanovic 856760599e Use properties for settings and save in json 2019-06-12 18:34:34 +02:00
David Shah 187db92b05 ecp5: Improve error message for bad chars in BRAM init strings 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-08 10:52:37 +01:00
Miodrag Milanovic d9b0bac248 Save top level attrs and store current step 2019-06-07 16:11:11 +02:00
Miodrag Milanovic 78e6631f76 Cleanup 2019-06-07 13:49:19 +02:00
Miodrag Milanovic 54175f9187 No need for this one 2019-06-07 13:24:16 +02:00
David Shah 15a1d4f582 ecp5: Use an attribute to store is_global 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-07 11:55:20 +01:00
Miodrag Milanovic 1093d7e122 WIP saving/loading attributes 2019-06-07 11:48:15 +02:00
Miodrag Milanovic d5d8213871 Added support for attributes/properties types 2019-06-01 15:52:32 +02:00
Tobias Müller ea91ea163e Use cmake's find_library to search for pytrellis. 2019-05-11 12:39:50 +02:00
David Shah 12f375a239 ecp5: Fix USRMCLK primitive 
Signed-off-by: David Shah <dave@ds0.me>
 2019-05-10 18:51:45 +01:00
David Shah 02ae21d8fc Add --placer option and refactor placer selection 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-24 11:10:20 +00:00
David Shah 23f2fff1c8 clangformat 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:39:05 +00:00
David Shah fcc3bb1495 ecp5: Speedup cell delay lookups 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah bd12c0a486 HeAP: Add PlacerHeapCfg 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah 7142db28a8 HeAP: Make HeAP placer optional 
A CMake option 'BUILD_HEAP' (default on) configures building of the
HeAP placer and the associated Eigen3 dependency.

Default for the iCE40 is SA placer, with --heap-placer to use HeAP

Default for the ECP5 is HeAP placer, as SA placer can take 1hr+ for
large ECP5 designs and HeAP tends to give better QoR. --sa-placer can
be used to use SA instead, and auto-fallback to SA if HeAP not built.

Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah 2e2f44c82e HeAP: tidying up 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah 8295f997ae HeAP: Use for ECP5 as well as iCE40 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah ea56dc9d08 HeAP: Add TAUCS wrapper and integration 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah 493d6c3fb9 Add Python helper functions for floorplanning 
Signed-off-by: David Shah <dave@ds0.me>
 2019-03-22 10:31:54 +00:00
David Shah 0279f63710
Merge pull request #243 from YosysHQ/ecp5lpf 
ecp5: Improve constraint-related error handling
 2019-02-28 15:01:42 +00:00
David Shah 8744c46ea0 ecp5: Fix handling of CRLFs and uppercase frequency units in LPF 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-27 22:54:32 +00:00
David Shah a2d906a3fd ecp5: Increase ripup penalty 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 18:08:26 +00:00
David Shah ba4150aecc ecp5: Add an error for mixed constrained/unconstrained IO 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 14:45:43 +00:00
David Shah 81b176e150 ecp5: Improve error handling and warning generation in LPF parser 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 14:40:38 +00:00
David Shah df79d94944 ecp5: DELAY fixes 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 11:49:25 +00:00
David Shah 95a85c8ea7 ecp5: Improve packing density 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 11:49:25 +00:00
David Shah a0fa164399 ecp5: Add criticality-based LUT permutation 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 11:49:25 +00:00
David Shah f363dd2d3c ecp5: Delay tuning 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 11:49:25 +00:00
David Shah 4ec2bd1e5d ecp5: Fix global clock routing with multiclock DPRAM 
Signed-off-by: David Shah <dave@ds0.me>
 2019-02-25 11:49:25 +00:00