8604b03008
interchange: Debug IO port validity check failures
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-12 11:40:23 +01:00
96a5885051
interchange: Place DIFFINBUF and IBUFCTRL for UltraScale+ IBUFDS
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-12 11:30:21 +01:00
fbd291deaf
interchange: update chipdb version
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-07-08 16:51:23 +02:00
dc0819b01a
interchange: reduce run-time to check dedicated interconnect
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-07-08 16:51:23 +02:00
31abefc8e4
interchange: Allow pseudo pip wires to overlap with bound site wires on the same net
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-06 10:38:08 +01:00
f64d06fa02
interchange: Improve search for PAD-attached bels
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-06 10:13:50 +01:00
6edc11de4d
interchange: tests: add obuftds test
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-07-06 09:57:26 +01:00
888a2462af
interchange: phys: skip only nets writing on disconnected out ports
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-07-02 16:12:53 +02:00
55c663f7ac
Merge pull request #746 from YosysHQ/gatecat/ic-can-invert-const
...
interchange: Handle canInvert PIPs when processing preferred constants
2021-07-01 15:28:24 +01:00
74ffe2c543
interchange: Handle canInvert PIPs when processing preferred constants
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-01 13:47:02 +01:00
f17643bc08
interchange: Handle case where routing source is a node
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-01 13:19:10 +01:00
ddff2e2e5e
Merge pull request #744 from YosysHQ/gatecat/const-in-macro
...
interchange: Fix handling of constants in macros
2021-07-01 13:12:38 +01:00
79ab283890
Merge pull request #743 from YosysHQ/gatecat/site-rsv-ports
...
interchange: Reserve site ports only reachable from dedicated routing
2021-07-01 13:12:29 +01:00
006a40a353
interchange: Fix handling of constants in macros
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-01 11:45:23 +01:00
dd7cfccbae
interchange: phys: do not output nets which have no users
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-07-01 12:36:05 +02:00
523ffbaa37
interchange: Reserve site ports only reachable from dedicated routing
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-07-01 11:28:12 +01:00
cfbd1dfa4d
interchange: fix dedicated interconnect exploration
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-06-30 20:04:23 +02:00
b3882f8324
interchange: Fix dedicated interconnect check when site is the same
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-30 11:48:51 +01:00
ef18590043
interchange: Place IO macro content based on routing
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-30 11:37:30 +01:00
2476f116bb
interchange: Track the macros that cells have been expanded from
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-29 14:48:47 +01:00
78c965141f
Merge pull request #736 from YosysHQ/gatecat/pp-multi-output
...
interchange: Allow site wires driven by more than one bel
2021-06-28 16:27:04 +01:00
65a4bce9ad
interchange: Allow site wires driven by more than one bel
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-28 14:55:56 +01:00
980a7013d2
interchange: Handle disconnected bel pins in dedicated interconnect
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-28 14:45:27 +01:00
0344fdcf8d
interchange: arch: move macro expansion step before ios packing
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-06-18 16:42:05 +02:00
ded32f3390
Merge pull request #728 from YosysHQ/gatecat/nexus-ram
...
interchange/nexus: Add RAM techmap rule and a RAM test
2021-06-15 17:39:23 +01:00
f9054190fd
interchange: fix phys net writer
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-06-15 14:07:20 +02:00
3e8f08895b
nexus: Add modified version of RAM test
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-15 11:07:40 +01:00
f42ad6b90c
nexus: Add PDPSC16K->PDPSC16K_MODE to remap rules
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-15 09:21:53 +01:00
377f56c151
interchange: Cope with undriven nets in more places
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-14 10:58:42 +01:00
2ffb081442
Fixing old emails and names in copyrights
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-12 13:22:38 +01:00
b65dbd5c9e
interchange: clusters: always get cell bel map and add asserts
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-06-11 11:19:01 +02:00
64b45848d7
interchange: run clang formatter
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-06-11 11:19:01 +02:00
d72c10cb6c
interchange: clusters: adjust comments
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-06-11 11:19:01 +02:00
e8191dc061
interchange: increase chipinfo version
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-06-11 11:19:01 +02:00
490ca794c5
interchange: tests: counter: emit carries for xc7
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-06-11 11:19:01 +02:00
104536b7aa
interchange: add support for generating BEL clusters
...
Clustering greatly helps the placer to identify and pack together
specific cells at the same site (e.g. LUT+FF), or cells that are chained through
dedicated interconnections (e.g. CARRY CHAINS)
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-06-11 11:19:01 +02:00
3cc58b3918
fpga_interchange: Add site router tests
...
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2021-06-11 08:43:30 +01:00
dcbb322447
Remove redundant code after hashlib move
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:20 +01:00
eca1a4cee4
Use hashlib in most remaining code
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:20 +01:00
ecc19c2c08
Using hashlib in arches
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 15:05:19 +01:00
579b98c596
Use hashlib for core netlist structures
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 14:27:56 +01:00
ff72454f83
Add hash() member functions
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-02 14:27:56 +01:00
0426ba4e87
interchange: Add LIFCL-40 EVN tests
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-06-01 09:52:40 +01:00
bae83857a3
interchange: Add macro parameter mapping
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-21 10:00:35 +01:00
64f5b1d031
interchange: Don't error out on missing cell ports
...
This is required for LUTRAM support, as the upper address bits of
RAMD64E etc are missing for shallower primitives.
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-21 10:00:35 +01:00
a146dbdb03
interchange: Add LUTRAM test
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-21 10:00:35 +01:00
2759480cb5
interchange: Preliminary implementation of macro expansion
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-21 10:00:35 +01:00
237b27e50b
interchange: Add macro param map rules to chipdb
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-21 10:00:35 +01:00
012b60c9ca
interchange: Add macro data to chipdb
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-21 10:00:35 +01:00
84359f39c5
interchange: phys: add site instance idstr for pseudo tile PIPs
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-05-19 18:48:54 +02:00
5a41d2070c
Run clangformat
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-16 16:25:05 +01:00
428b56570d
interchange: pseudo pips: fix illegal tile pseudo PIPs
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-05-14 12:17:53 +02:00
8c468acff8
interchange: site router: add valid pips list to check during routing
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-05-13 11:00:42 +02:00
fd93697a2d
interchange: arch: do not allow site pips within sites
...
During general routing, the only site pips that can be allowed are those
which connect a site wire to the routing interface.
This might be too restrictive when dealing with architectures that
require more than one site PIPs to route from a driver within a site to the routing
interface (which is something that should be allowed in the
interchange).
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-05-12 18:28:22 +02:00
7a1a95a2d6
interchange: Fix bounding box computation
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-11 13:02:23 +01:00
45618faf36
interchange: site router: fix log messages
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-05-10 14:20:54 +02:00
beff2b912c
interchange: site router: fix illegal site thru paths
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-05-10 14:05:46 +02:00
9a1cad85fe
interchange: Adding a basic global buffer placer
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-07 10:28:59 +01:00
9b3fb00908
interchange: Initial global routing implementation
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-07 10:28:56 +01:00
b8c8200683
interchange: Add more global cell info
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-07 10:25:18 +01:00
0d6be6f474
Add stub cluster API impl for remaining arches
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-05-06 13:12:52 +01:00
49caad0b7b
interchange/nexus: Add counter example
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-30 14:15:37 +01:00
dcb09ec8de
interchange: Implement getWireType
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-30 11:07:31 +01:00
ecf24201ec
interchange: Add wire types to chipdb
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-30 11:07:14 +01:00
3fd1ee7757
Merge pull request #683 from antmicro/interchange-allow-loc-keyword
...
interchange: allow LOC keyword in XDC files
2021-04-20 14:12:14 +01:00
d1548ed317
interchange: allow LOC keyword in XDC files
...
Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
2021-04-20 14:35:15 +02:00
18459a9e4c
interchange: Handle disconnected/missing cell pins
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-19 10:46:35 +01:00
872b3aa63d
interchange: Add default cell connections to chipdb
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-19 10:16:26 +01:00
d4aac6586c
Add Python bindings for placement tests
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-15 10:00:45 +01:00
8f5185c381
Merge pull request #678 from acomodi/initial-fasm-generation
...
interchange: add FASM generation target and clean-up tests
2021-04-14 14:28:01 +01:00
dfc9c3df8c
interchange: add FASM generation target and clean-up tests
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-04-14 14:36:07 +02:00
4e346ecfba
Hash table refactoring
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-14 10:30:19 +01:00
06e54f08e6
interchange: Allow pseudo-cells with no input pins
...
These are used for the LUT-as-GND-driver pseudo-pips in the Nexus arch,
which will probably be required for UltraScale too.
Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-13 10:58:41 +01:00
fc15105643
clangformat
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-12 10:26:39 +01:00
93e34b8754
interchange: Disambiguate cell and bel pins when creating Vcc ties
...
The pins created for tieing to Vcc were being named after the bel pin,
relying on the fact that Xilinx names cell and bel pins differently for
LUTs. This isn't true for Nexus devices which uses the same names for
both, and was causing a failure as a result.
This uses a "PHYS_" prefix that's highly unlikely to appear in a cell
pin name to disambiguate.
Signed-off-by: gatecat <gatecat@ds0.me>
2021-04-09 10:26:32 +01:00
ae2f7551c1
[interchange] Provide estimateDelay when USE_LOOKAHEAD is not defined.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-04-06 10:42:05 -07:00
3200026e1f
[interchange] Remove requirement to have wire_lut.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-04-06 10:42:05 -07:00
c2a6f6ce62
[interchange] Fix invalid use of local variables due to refactoring.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-04-06 10:42:05 -07:00
8773c645ca
[interchange] Prevent site router from generating incorrect LUTs.
...
The previous logic tied LUT input pins to VCC if a wire was unplacable.
This missed a case where the net was present to the input of the LUT,
but a wire was still not legal. This case is now prevented by tying the
output of the LUT to an unused net.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-04-06 10:42:05 -07:00
c11ad31393
[interchange] Scale edge cost of pseudo pips.
...
Previous pseudo pips were the same cost as regular pips, but this is
definitely too fast, and meant that the router was prefering them.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-04-06 10:42:05 -07:00
9b82ded77b
[interchange] Fix missing inline methods in site_arch.impl.h
...
getBelPinWire and getBelPinType are marked as always inline, but were
not defined in a header.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-04-06 10:42:05 -07:00
90aa1d3b7e
[interchange] Disallow site edges during general routing.
...
This prevents the general router from routing through sites, which is
not legal in FPGA interchange.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-04-06 10:42:05 -07:00
0d41fff3a7
[interchange] Add crude pseudo pip model.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-04-06 10:42:05 -07:00
ff449ca997
Merge pull request #661 from litghost/document_site_router
...
[interchange] Add some documentation for the site router.
2021-04-06 09:20:03 +01:00
8e0d8df791
Merge pull request #657 from acomodi/interchange-counter-multi-board
...
interchange: counter: testing on multiple boards
2021-04-06 08:12:02 +01:00
4301e4705b
[interchange] Add some documentation for the site router.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-04-05 15:15:48 -07:00
009d3b64b6
[interchange] Update to v6 of FPGA interchange chipdb.
...
Changes:
- Adds LUT output pin to LutBelPOD.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-04-01 15:24:06 -07:00
366f8782cb
interchange: counter: testing on multiple boards
...
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-04-01 10:23:07 +02:00
ec98fee1ee
Merge pull request #646 from YosysHQ/gatecat/nexus-cmake
...
fpga_interchange: Add CMake support for Nexus/prjoxide
2021-03-31 15:14:51 +01:00
3678eff5dc
interchange: Fix nexus cmake review comments
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-31 10:11:09 +01:00
8675945b26
Fix bug where DedicateInterconnect incorrectly allows some placement.
...
This occurs when the driver pin and sink pin are part of the same site,
but not reachable with site routing only.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-30 13:24:39 -07:00
7e47af1085
[interchange] Fix site pip check for drivers.
...
Previous code allowed router to entire sites with no sinks.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-30 10:04:18 -07:00
a003aae7c2
interchange: Split xc7 and nexus chipdb cmake
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-30 16:31:51 +01:00
ecfaae7f9e
interchange: Add Nexus LUT test
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-30 16:31:51 +01:00
b6b8959397
interchange: Add Nexus to CI
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-30 16:31:51 +01:00
3cb5e81d50
interchange: Add CMake support for Nexus/prjoxide
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-30 16:31:51 +01:00
8863b962fd
interchange: Fix illegal placements
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-30 15:28:19 +01:00
692d7dc26d
Merge pull request #645 from litghost/add_counter_and_ram
...
FPGA interchange: Add counter and ram tests
2021-03-29 18:23:16 +01:00
b5ba3ee9ee
interchange: add archcheck tests to all-device-test target
...
This increases parallelism and should make the FPGA interchange CI
faster
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-03-26 15:11:03 +01:00
f33d02dca9
Update README with latest develpment progress.
...
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-25 17:56:15 -07:00
gatecat
Alessandro Comodi
Tomasz Michalak
Jan Kowalewski
Keith Rothman