e7d81913a4
Add "checkPipAvailForNet" to Arch API.
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This is important for distiguishing valid pseudo pips in the FPGA
interchange arch. This also avoids a double or triple lookup of
pip->net map.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-22 09:17:55 -07:00
db12a83ced
Add pseudo pip data to chipdb (with schema bump).
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-22 09:33:12 +00:00
2cd5bacca0
Refactor header structures in FPGA interchange Arch.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-19 21:36:06 -07:00
351ca3b5ea
Use NEXTPNR_NAMESPACE macro's now that headers are seperated.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-03-15 18:49:12 +00:00
fba71bd182
clangformat
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-03 10:39:47 +00:00
cfa449c3f3
Initial LUT rotation logic.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-26 11:01:22 -08:00
a30043c8da
Fix assorted bugs in FPGA interchange.
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Fixes:
- Only use map constant pins during routing, and not during placement.
- Unmapped cell ports have no BEL pins.
- Fix SiteRouter congestion not taking into account initial expansion.
- Fix psuedo-site pip output.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
184665652e
Finish dedicated interconnect implementation.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
5574455d2a
Working FF example now that constant merging is done.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
2fc353d559
Add initial logic for handling dedicated interconnect situations.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
5c6e231412
Remove some signedness warnings.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:28 -08:00
40df4f4f65
Add initial constant network support to FPGA interchange arch.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-23 14:09:27 -08:00
7922b3bfc4
Replace DelayInfo with DelayPair/DelayQuad
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This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.
This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.
While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.
Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-19 11:31:33 +00:00
4766e889c0
Add some utility methods for site instance access.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-18 13:26:52 -08:00
558a753d3d
Refactor "get only from iterator" to a utility.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:17 -08:00
f9bd692f75
Change how package pin IO sites are selected.
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The first site type that matches is now selected, under the premise that
the early site types are more general.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:16 -08:00
7c1544f4d8
Continue fixes.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:16 -08:00
c385321248
Add initial site router.
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This site router likely cannot handle the full problem space. It may
need to be replaced with a more generalize approach as testing
continues.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:16 -08:00
a7421399f7
Working on standing up initial constraints system.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-17 12:03:16 -08:00
399c24c805
clangformat
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Signed-off-by: gatecat <gatecat@ds0.me>
2021-02-17 10:45:23 +00:00
26a187e5eb
Require `--package` when arch BBA contains multiple packages.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-16 14:00:01 -08:00
bb4fa7af5b
[FPGA Interchange] Add Cell -> BEL Pin maps.
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This also expands the FPGA interchange Arch BBA to include placement
constraints, but doesn't implement them yet.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-16 09:37:19 -08:00
664407089b
Add FPGA interchange frontend and backend.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-15 09:54:58 -08:00
82ab3c1aad
Run "make clangformat".
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-12 10:31:05 -08:00
c96d0f225c
Refactor XDC parser into a little class for testing purposes.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-12 10:31:04 -08:00
a0bd313139
Add FPGA interchange XDC parser.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-12 10:31:04 -08:00
9deb9e6e85
interchange: Base on ArchAPI
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Signed-off-by: D. Shah <dave@ds0.me>
2021-02-08 10:41:03 +00:00
a0ee42833b
Add RelSlice::ssize and use it when comparing with signed ints.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-05 10:12:13 -08:00
9557047e5e
Move all string data into BBA file.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-05 09:22:55 -08:00
ca32e935a6
Use RelSlice instead of RelPtr in cases where sizes are present.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:34 -08:00
f1ee2fde58
Update APIs to conform to style guide.
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- Change non-Arch methods to snake_case
- Adds some utility functions to for accessing bel_data.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:34 -08:00
22c3c9c303
Update copywrite headers.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:33 -08:00
d8fa9d7f36
Fix warnings with signed/unsigned.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:33 -08:00
0b911e484c
Run "make clangformat".
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:33 -08:00
78737ab01d
Update FPGA interchange to use IdStringList.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:33 -08:00
4a62c8c2eb
Start adding data for placement constraint solving.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:33 -08:00
cd41c4001e
Add initial updates to FPGA interchange arch for BEL buckets.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:33 -08:00
67dc19bb57
Address review comments.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:33 -08:00
5a89dc58e1
Fix BBA import bugs.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:33 -08:00
1dd24f6461
Assorted fixes to new FPGA interchange based arch.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:33 -08:00
6e68e8f097
Initial compiling version.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:32 -08:00
561b519716
Initial FPGA interchange (which is just a cut-down xilinx arch).
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2021-02-04 16:38:32 -08:00
Keith Rothman
gatecat
D. Shah