mirror of https://github.com/YosysHQ/nextpnr.git
handle pip masks
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parent
42a20eacb7
commit
07e261094c
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@ -153,13 +153,6 @@ struct BitstreamBackend
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void export_connection(ChipConfig &cc, PipId pip)
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{
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const auto &extra_data = *uarch->pip_extra_data(pip);
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if (extra_data.type == PipExtra::PIP_EXTRA_MUX) {
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IdString name = IdString(extra_data.name);
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if (name==ctx->id("PASS")) {
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auto n = ctx->getPipName(pip);
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printf("PASS %s %s -> %s\n", n[0].c_str(ctx), n[2].c_str(ctx), n[1].c_str(ctx));
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}
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}
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if (extra_data.type == PipExtra::PIP_EXTRA_MUX && (extra_data.flags & MUX_VISIBLE)) {
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IdString name = IdString(extra_data.name);
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CfgLoc loc = get_config_loc(pip.tile);
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@ -127,6 +127,25 @@ enum ClusterPlacement
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PLACE_DB_CONSTR = 32,
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};
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enum PipMask
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{
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IS_MULT = 1 << 0,
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IS_ADDF = 1 << 1,
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IS_COMP = 1 << 2,
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C_SELX = 1 << 3,
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C_SELY1 = 1 << 4,
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C_SELY2 = 1 << 5,
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C_SEL_C = 1 << 6,
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C_SEL_P = 1 << 7,
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C_Y12 = 1 << 8,
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C_CX_I = 1 << 9,
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C_CY1_I = 1 << 10,
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C_CY2_I = 1 << 11,
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C_PX_I = 1 << 12,
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C_PY1_I = 1 << 13,
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C_PY2_I = 1 << 14,
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};
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struct PllCfgRecord
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{
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double weight;
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@ -308,7 +308,8 @@ void GateMateImpl::postPlace()
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repack();
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ctx->assignArchInfo();
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used_cpes.resize(ctx->getGridDimX() * ctx->getGridDimY());
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passtrough.resize(ctx->getGridDimX() * ctx->getGridDimY());
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pip_data = std::vector<uint32_t>(ctx->getGridDimX() * ctx->getGridDimY());
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//pip_mask = std::vector<uint32_t>(ctx->getGridDimX() * ctx->getGridDimY());
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for (auto &cell : ctx->cells) {
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// We need to skip CPE_MULT since using CP outputs is mandatory
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// even if output is actually not connected
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@ -318,17 +319,32 @@ void GateMateImpl::postPlace()
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marked_used = true;
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if (marked_used)
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used_cpes[cell.second.get()->bel.tile] = true;
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int cy2_i = int_or_default(cell.second->params, id_C_CY2_I, 0);
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if (cell.second.get()->type == id_CPE_MULT || cy2_i == 1)
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passtrough[cell.second.get()->bel.tile] = true;
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uint32_t mask = 0;
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if (cell.second.get()->type == id_CPE_MULT) mask |= PipMask::IS_MULT;
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if (cell.second.get()->type == id_CPE_ADDF) mask |= PipMask::IS_ADDF;
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if (cell.second.get()->type == id_CPE_ADDF2) mask |= PipMask::IS_ADDF;
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if (cell.second.get()->type == id_CPE_COMP) mask |= PipMask::IS_COMP;
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if (int_or_default(cell.second->params, id_C_SELX, 0)) mask |= PipMask::C_SELX;
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if (int_or_default(cell.second->params, id_C_SELY1, 0)) mask |= PipMask::C_SELY1;
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if (int_or_default(cell.second->params, id_C_SELY2, 0)) mask |= PipMask::C_SELY2;
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if (int_or_default(cell.second->params, id_C_SEL_C, 0)) mask |= PipMask::C_SEL_C;
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if (int_or_default(cell.second->params, id_C_SEL_P, 0)) mask |= PipMask::C_SEL_P;
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if (int_or_default(cell.second->params, id_C_Y12, 0)) mask |= PipMask::C_Y12;
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if (int_or_default(cell.second->params, id_C_CX_I, 0)) mask |= PipMask::C_CX_I;
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if (int_or_default(cell.second->params, id_C_CY1_I, 0)) mask |= PipMask::C_CY1_I;
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if (int_or_default(cell.second->params, id_C_CY2_I, 0)) mask |= PipMask::C_CY2_I;
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if (int_or_default(cell.second->params, id_C_PX_I, 0)) mask |= PipMask::C_PX_I;
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if (int_or_default(cell.second->params, id_C_PY1_I, 0)) mask |= PipMask::C_PY1_I;
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if (int_or_default(cell.second->params, id_C_PY2_I, 0)) mask |= PipMask::C_PY2_I;
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pip_data[cell.second.get()->bel.tile] = mask;
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}
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}
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bool GateMateImpl::checkPipAvail(PipId pip) const
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{
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const auto &extra_data = *pip_extra_data(pip);
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if (extra_data.type == PipExtra::PIP_EXTRA_MUX && (extra_data.flags & MUX_PASSTROUGH)) {
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//printf("pip: %s\n",ctx->getPipName(pip)[1].c_str(ctx));
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if (passtrough[pip.tile])
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if (extra_data.type == PipExtra::PIP_EXTRA_MUX && (extra_data.mask != 0)) {
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if ((pip_data[pip.tile] & extra_data.mask) != extra_data.data)
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return false;
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}
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if (extra_data.type != PipExtra::PIP_EXTRA_MUX || (extra_data.flags & MUX_ROUTING) == 0)
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@ -96,7 +96,8 @@ struct GateMateImpl : HimbaechelAPI
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pool<IdString> multiplier_a_passthru_uppers;
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pool<IdString> multiplier_zero_drivers;
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std::vector<bool> used_cpes;
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std::vector<bool> passtrough;
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std::vector<uint32_t> pip_data;
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std::vector<uint32_t> pip_mask;
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int fpga_mode;
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int timing_mode;
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std::map<const NetInfo *, int> global_signals;
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