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wip
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@ -153,6 +153,13 @@ struct BitstreamBackend
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void export_connection(ChipConfig &cc, PipId pip)
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{
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const auto &extra_data = *uarch->pip_extra_data(pip);
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if (extra_data.type == PipExtra::PIP_EXTRA_MUX) {
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IdString name = IdString(extra_data.name);
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if (name==ctx->id("PASS")) {
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auto n = ctx->getPipName(pip);
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printf("PASS %s %s -> %s\n", n[0].c_str(ctx), n[2].c_str(ctx), n[1].c_str(ctx));
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}
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}
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if (extra_data.type == PipExtra::PIP_EXTRA_MUX && (extra_data.flags & MUX_VISIBLE)) {
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IdString name = IdString(extra_data.name);
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CfgLoc loc = get_config_loc(pip.tile);
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@ -43,6 +43,8 @@ NPNR_PACKED_STRUCT(struct GateMatePipExtraDataPOD {
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uint8_t plane;
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uint8_t dummy1;
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uint16_t dummy2;
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uint32_t data;
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uint32_t mask;
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});
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NPNR_PACKED_STRUCT(struct GateMateBelPinConstraintPOD {
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@ -74,6 +74,8 @@ class PipExtraData(BBAStruct):
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value: int = 0
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invert: int = 0
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plane: int = 0
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data: int = 0
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mask: int = 0
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def serialise_lists(self, context: str, bba: BBAWriter):
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pass
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@ -86,6 +88,8 @@ class PipExtraData(BBAStruct):
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bba.u8(self.plane)
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bba.u8(0)
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bba.u16(0)
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bba.u32(self.data)
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bba.u32(self.mask)
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@dataclass
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class BelPinConstraint(BBAStruct):
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@ -313,7 +317,7 @@ def main():
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mux_flags |= MUX_ROUTING
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if mux.name == "PASS":
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mux_flags |= MUX_PASSTROUGH
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pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id(mux.name), mux.bits, mux.value, mux_flags, plane)
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pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id(mux.name), mux.bits, mux.value, mux_flags, plane, mux.data, mux.mask)
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if type_name in new_wires:
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for wire in sorted(new_wires[type_name]):
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delay = wire_delay[wire]
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