Tim Edwards
c45d51e950
Tracked down and fixed problems with implicit pins in verilog (pins
...
that are not declared in the verilog netlist because they don't
connect to anything, and their presence is not required by verilog
syntax) and the printing of proxy pins created to act as placeholders
for those implicit pins. Also removed the pinting of the "disconnected
pin" messages for black-box modules (since by definition they have
disconnected pins, because black-box modules have no contents).
2020-07-31 12:22:50 -04:00
..
2016-06-23 10:13:18 -04:00
2015-05-18 09:27:46 -04:00
2016-10-24 13:42:08 -04:00
2016-10-24 13:42:08 -04:00
2015-05-18 09:27:46 -04:00
2016-10-24 13:42:08 -04:00
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2018-06-17 15:05:15 -04:00
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2018-04-12 17:09:10 -04:00
2020-03-26 09:04:52 -04:00
2015-05-18 09:27:46 -04:00
2018-06-17 15:05:15 -04:00
2018-01-26 11:56:41 -05:00
2015-05-18 09:27:46 -04:00
2018-04-12 17:09:10 -04:00
2020-07-31 12:22:50 -04:00
2020-02-10 09:11:34 -05:00
2020-07-24 20:50:07 -04:00
2020-07-24 20:50:07 -04:00
2018-11-19 08:12:12 -05:00
2019-01-09 20:26:38 -05:00
2018-06-17 15:05:15 -04:00
2020-07-30 22:51:34 -04:00
2019-01-09 20:26:38 -05:00
2015-05-18 09:27:46 -04:00
2015-05-18 09:27:46 -04:00
2016-10-24 13:42:08 -04:00
2015-05-18 09:27:46 -04:00
2015-05-18 09:27:46 -04:00
2015-05-18 09:27:46 -04:00
2020-07-31 12:22:50 -04:00
2015-05-18 09:27:46 -04:00
2015-05-18 09:27:46 -04:00
2015-05-18 09:27:46 -04:00
2020-07-30 22:51:34 -04:00
2015-05-18 09:27:46 -04:00
2015-05-18 09:27:46 -04:00
2015-05-18 09:27:46 -04:00
2020-07-30 22:51:34 -04:00
2015-05-18 09:27:46 -04:00
2018-01-26 11:56:41 -05:00
2015-05-18 09:27:46 -04:00
2017-01-07 06:56:51 -05:00
2015-05-18 09:27:46 -04:00