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R. Timothy Edwards
f29452e550
pin assignment when a verilog input file declares a signal "bundle"
with only one signal in it. The solution is to detect bundles which
have only one component in them, and remove the bundle delimiters
("{...}") so that the pin connection is treated as a simple signal
or vector.
2 lines
8 B
Plaintext
2 lines
8 B
Plaintext
1.5.320
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