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An example found by Leo Moser showed that netgen makes an incorrect pin assignment when a verilog input file declares a signal "bundle" with only one signal in it. The solution is to detect bundles which have only one component in them, and remove the bundle delimiters ("{...}") so that the pin connection is treated as a simple signal or vector.
2026-05-21 20:19:24 +02:00
1.5.320