Merge branch 'master' into netgen-1.5

Makefile

@@ -9,7 +9,7 @@ MODULES = base
 MAKEFLAGS =
 INSTALL_CAD_DIRS = lib doc
 
--include defs.mak
+include defs.mak
 
 all:	$(ALL_TARGET)
 

VERSION

@@ -1 +1 @@
-1.5.158
+1.5.135

base/flatten.c

@@ -259,7 +259,7 @@ int flattenInstancesOf(char *name, int fnum, char *instance)
   struct  nlist *ChildCell;
   struct objlist *tmp, *ob2, *ob3;
   int	notdone, rnodenum;
-  char	tmpstr[1024];
+  char	tmpstr[200];
   int	nextnode, oldmax, numflat = 0;
 #if !OLDPREFIX
   int     prefixlength;
@@ -1166,7 +1166,7 @@ struct nlist *cleanuppins(struct hashlist *p, void *clientdata)
           while (ob && obt && (ob->type > FIRSTPIN || ob == firstpin) &&
 			ob->model.class != NULL) {
 	     nob = ob->next;
-	     if ((obt->type == PORT) && (obt->node == -2)) {
+	     if ((obt->type == PORT) && (obt->node == -1)) {
 
 	        /* Remove this pin */
 
@@ -1238,7 +1238,7 @@ int CleanupPins(char *name, int filenum)
 
    for (ob = ThisCell->cell; ob != NULL; ob = ob->next) {
       if (ob->type != PORT) break;
-      if (ob->node == -2) {
+      if (ob->node == -1) {
 	 needscleanup = 1;
 	 break;
       }
@@ -1265,7 +1265,7 @@ int CleanupPins(char *name, int filenum)
       }
       else if (ob->type != PORT) break;
       nob = ob->next;
-      if (ob->node == -2) {
+      if (ob->node == -1) {
 	 if (lob == NULL) {
 	    ThisCell->cell = ob->next;
 	 }
@@ -1539,7 +1539,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
 	/* (it without regard to cell1) improves the matching.	*/
 
 	else if ((ecomp->num1 != ecomp->num2) && (ecomp->cell2 != NULL) &&
-			(ecomp->num2 != 0) && (ecomp->cell2->class == CLASS_SUBCKT)) {
+			(ecomp->cell2->class == CLASS_SUBCKT)) {
 	    ecomp->add2 = -ecomp->num2;
 	    match = 1;
 	    for (ob2 = ecomp->cell2->cell; ob2; ob2 = ob2->next) {
@@ -1597,7 +1597,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
 	/* (it without regard to cell1) improves the matching.	*/
 
 	else if ((ecomp->num1 != ecomp->num2) && (ecomp->cell1 != NULL) &&
-			(ecomp->num1 != 0) && (ecomp->cell1->class == CLASS_SUBCKT)) {
+			(ecomp->cell1->class == CLASS_SUBCKT)) {
 	    ecomp->add1 = -ecomp->num1;
 	    match = 1;
 	    for (ob2 = ecomp->cell1->cell; ob2; ob2 = ob2->next) {

base/netcmp.h

@@ -7,10 +7,6 @@ extern struct nlist *Circuit1;
 extern struct nlist *Circuit2;
 
 extern int ExhaustiveSubdivision;
-extern int FastSymmetryBreaking;
-
-extern int left_col_end;
-extern int right_col_end;
 
 #ifdef TCL_NETGEN
 #include <tcl.h>

base/netfile.c

@@ -289,7 +289,6 @@ int GetNextLineNoNewline(char *delimiter)
     char *newbuf;
     int testc;
     int nested = 0;
-    int llen;
 
     if (feof(infile)) return -1;
 
@@ -302,33 +301,20 @@ int GetNextLineNoNewline(char *delimiter)
 
 	if (linesize == 0) {
 	    /* Allocate memory for line */
-	    linesize = 2000;
-	    line = (char *)MALLOC(linesize + 1);
-	    linetok = (char *)MALLOC(linesize + 1);
+	    linesize = 500;
+	    line = (char *)MALLOC(linesize);
+	    linetok = (char *)MALLOC(linesize);
 	}
 	fgets(line, linesize, infile);
-	/* Immediately resolve backslash-EOL */
-	llen = strlen(line);
-	while ((llen > 1) && (llen < linesize - 1) && *(line + llen - 2) == '\\') {
-	    *(line + llen - 2) = '\n';
-	    fgets(line + llen - 1, linesize - llen + 1, infile);
-	    llen = strlen(line);
-	}
-	while (llen == linesize - 1) {
-	    newbuf = (char *)MALLOC(linesize + 501);
+	while (strlen(line) == linesize - 1) {
+	    newbuf = (char *)MALLOC(linesize + 500);
 	    strcpy(newbuf, line);
 	    FREE(line);
 	    line = newbuf;
 	    fgets(line + linesize - 1, 501, infile);
-	    llen = strlen(line);
-	    while ((llen > 1) && (llen < linesize - 1) && *(line + llen - 2) == '\\') {
-		*(line + llen - 2) = '\n';
-		fgets(line + llen - 1, linesize - llen + 1, infile);
-		llen = strlen(line);
-	    }
 	    linesize += 500;
 	    FREE(linetok);
-	    linetok = (char *)MALLOC(linesize + 1);
+	    linetok = (char *)MALLOC(linesize);
 	}
 
 	/* Check for substitutions (verilog only).  Make sure linetok is    */
@@ -343,7 +329,7 @@ int GetNextLineNoNewline(char *delimiter)
 	    for (s = line; *s != '\0'; s++) {
 		if (*s == '`') {
 		    w = s + 1;
-		    while (isalnum(*w) || (*w == '_') || (*w == '$')) w++;
+		    while (isalnum(*w)) w++;
 		    e = *w;
 		    *w = '\0';
 		    kl = (struct property *)HashLookup(s + 1, definitions);
@@ -379,7 +365,7 @@ int GetNextLineNoNewline(char *delimiter)
 	    for (s = line; *s != '\0'; s++) {
 		if (*s == '`') {
 		    w = s + 1;
-		    while (isalnum(*w) || (*w == '_') || (*w == '$')) w++;
+		    while (isalnum(*w)) w++;
 		    e = *w;
 		    *w = '\0';
 		    kl = (struct property *)HashLookup(s + 1, definitions);
@@ -510,24 +496,6 @@ void GetNextLine(char *delimiter)
     } while (nexttok == NULL);
 }
 
-/*----------------------------------------------------------------------*/
-/* Return a pointer to the line at the position of nexttok		*/
-/* This is used only when returning the entire line, untokenized, and	*/
-/* is only called by the verilog read routine when reading the value of	*/
-/* a `define statement.							*/
-/*----------------------------------------------------------------------*/
-
-char *GetLineAtTok()
-{
-    char *lpos;
-
-    if (nexttok == NULL) return NULL;
-    if (line == NULL) return NULL;
-
-    lpos = strstr(line, nexttok);
-    return lpos;
-}
-
 /*----------------------------------------------------------------------*/
 /* if nexttok is already NULL, force scanner to read new line		*/
 /*----------------------------------------------------------------------*/
@@ -705,7 +673,6 @@ char *strdtok(char *pstring, char *delim1, char *delim2)
     /* accordingly (needs to be done).						*/
 
     if (*s == '\\') {
-        s++;
         while (*s != '\0') {
 	    if ((*s == ' ') || (*s == '\\')) {
 		s++;
@@ -798,7 +765,7 @@ int OpenParseFile(char *name, int fnum)
   FILE *locfile;
   struct filestack *newfile;
 
-  locfile = fopen(name, "r");
+  locfile = fopen(name,"r");
   linenum = 0;
   /* reset the token scanner */
   nexttok = NULL;  
@@ -883,12 +850,7 @@ char *ReadNetlist(char *fname, int *fnum)
       {SPICE_EXTENSION, ReadSpice},
       {SPICE_EXT2, ReadSpice},
       {SPICE_EXT3, ReadSpice},
-      {SPICE_EXT4, ReadSpice},
-      {SPICE_EXT5, ReadSpice},
-      {SPICE_EXT6, ReadSpice},
-      {SPICE_EXT7, ReadSpice},
       {VERILOG_EXTENSION, ReadVerilog},
-      {SYS_VERILOG_EXTENSION, ReadVerilog},
       {NETGEN_EXTENSION, ReadNetgenFile},
       {NULL, NULL}
     };

base/netfile.h

@@ -9,16 +9,11 @@
 #define SIM_EXTENSION ".sim"
 #define SPICE_EXTENSION ".spice"
 #define SPICE_EXT2 ".spc"
-#define SPICE_EXT3 ".sp"
-#define SPICE_EXT4 ".spi"
-#define SPICE_EXT5 ".fspc"
-#define SPICE_EXT6 ".cir"
-#define SPICE_EXT7 ".ckt"
+#define SPICE_EXT3 ".fspc"
 #define NETGEN_EXTENSION ".ntg"
 #define CCODE_EXTENSION ".c.code"
 #define ESACAP_EXTENSION ".esa"
 #define VERILOG_EXTENSION ".v"
-#define SYS_VERILOG_EXTENSION ".sv"
 
 #define LINELENGTH 80
 
@@ -36,7 +31,6 @@ extern struct hashdict *definitions;
 extern char *nexttok;
 #define SKIPTO(a) do {SkipTok(NULL);} while (!match(nexttok,a))
 extern char *strdtok(char *pstring, char *delim1, char *delim2);
-extern char *GetLineAtTok();
 extern void SkipTok(char *delimiter);
 extern void SkipTokNoNewline(char *delimiter);
 extern void SkipTokComments(char *delimiter);

base/objlist.c

@@ -289,7 +289,7 @@ static struct hashdict cell_dict;
 void InitCellHashTable(void)
 {
     hashfunc = hash;
-    matchfunc = NULL;
+    matchfunc = match;
     matchintfunc = matchfile;
     InitializeHashTable(&cell_dict, CELLHASHSIZE);
 }
@@ -1112,17 +1112,13 @@ void FreeObjectAndHash(struct objlist *ob, struct nlist *ptr)
 
 /***************  GENERAL UTILITIES ****************************/
 
-int NumberOfPorts(char *cellname, int file)
+int NumberOfPorts(char *cellname)
 {
   struct nlist *tp;
   struct objlist *ob;
   int ports;
 
-  if (file == -1)
-    tp = LookupCell(cellname);
-  else
-    tp = LookupCellFile(cellname, file);
-
+  tp = LookupCell(cellname);
   if (tp == NULL) return(0);
   ports = 0;
   for (ob = tp->cell; ob != NULL; ob = ob->next)

base/objlist.h

@@ -242,7 +242,7 @@ extern void FreeObjectAndHash(struct objlist *ob, struct nlist *ptr);
 extern void FreePorts(char *cellname);
 extern struct IgnoreList *ClassIgnore;
 
-extern int NumberOfPorts(char *cellname, int file);
+extern int NumberOfPorts(char *cellname);
 extern struct objlist *InstanceNumber(struct nlist *tp, int inst);
 
 extern struct objlist *List(char *list_template);

base/place.c

@@ -929,7 +929,7 @@ void ToggleDebug(void)
 void DescribeCell(char *name, int detail)
 {
   Printf("Cell: %s contains %d instances, %d nodes and %d ports\n", name, 
-	 NumberOfInstances(name),  RenumberNodes(name), NumberOfPorts(name, -1));
+	 NumberOfInstances(name),  RenumberNodes(name), NumberOfPorts(name));
   PrintEmbeddingTree(stdout,name,detail);
 }
 

base/query.c

@@ -801,16 +801,9 @@ void DescribeInstance(char *name, int file)
   {
     if (ob->node > nodemax) nodemax = ob->node;
     else if ((ob->node == -1) && (ob->model.port != PROXY)) {
-
-      /* All black-box modules and placeholders by definition have all	*/
-      /* disconnected pins, so don't report those.			*/
-
-      if (!(tp->flags & CELL_PLACEHOLDER) && (tp->class != CLASS_MODULE))
-      {
-	if (disconnectednodes == 0) Fprintf(stderr, "\n");
-        disconnectednodes++;
-        Fprintf(stderr, "Cell %s disconnected node: %s\n", tp->name, ob->name);
-      }
+      if (disconnectednodes == 0) Fprintf(stderr, "\n");
+      disconnectednodes++;
+      Fprintf(stderr, "Cell %s disconnected node: %s\n", tp->name, ob->name);
     }
   }
   instlist = (unsigned char *) CALLOC((nodemax + 1), sizeof(unsigned char));
@@ -907,7 +900,7 @@ void PrintLeavesInCell(char *cellname, int filenum)
   np->dumped = 1;
 
   if (np->class != CLASS_SUBCKT) {
-    Printf("%s; %d ports; Primitive.\n", cellname, NumberOfPorts(cellname, filenum));
+    Printf("%s; %d ports; Primitive.\n", cellname, NumberOfPorts(cellname));
     return;
   }
 
@@ -920,7 +913,7 @@ void PrintLeavesInCell(char *cellname, int filenum)
       am_a_leaf = 0;
     }
 
-  if (am_a_leaf) Printf("%s; %d ports\n", cellname, NumberOfPorts(cellname, filenum));
+  if (am_a_leaf) Printf("%s; %d ports\n", cellname, NumberOfPorts(cellname));
   return;
 }
 
@@ -1070,7 +1063,7 @@ void Query(void)
       ActelLib();
       break;
     case 'S':
-      promptstring("Read SPICE (.spice) file? ", repstr);
+      promptstring("Read SPICE (.ckt) file? ", repstr);
       ReadSpice(repstr, &filenum);
       break;
     case 'V':

base/spice.c

@@ -1883,36 +1883,20 @@ char *ReadSpiceTop(char *fname, int *fnum, int blackbox)
   CurrentCell = NULL;
 
   if ((filenum = OpenParseFile(fname, *fnum)) < 0) {
+    char name[100];
 
-    if (strrchr(fname, '.') == NULL) {
-      char name[1024];
-      SetExtension(name, fname, SPICE_EXTENSION);
-      if ((filenum = OpenParseFile(name, *fnum)) < 0) {
-        Fprintf(stderr, "Error in SPICE file read: No file %s\n", name);
-        *fnum = filenum;
-        return NULL;
-      }
-    }    
-    else {
-      Fprintf(stderr, "Error in SPICE file read: No file %s\n", fname);
+    SetExtension(name, fname, SPICE_EXTENSION);
+    if ((filenum = OpenParseFile(name, *fnum)) < 0) {
+      Fprintf(stderr,"Error in SPICE file read: No file %s\n",name);
       *fnum = filenum;
       return NULL;
-    }
+    }    
   }
 
-  /* Make sure all SPICE file reading is case insensitive   */
-  /* BUT if a verilog file was read before it, then it will */
-  /* be forced to be case sensitive, caveat end-user.	    */
-
-  if (matchfunc == match) {
-      Printf("Warning:  A case-sensitive file has been read and so the "
-                "SPICE netlist must be treated case-sensitive to match.\n");
-  }
-  else {
-      matchfunc = matchnocase;
-      matchintfunc = matchfilenocase;
-      hashfunc = hashnocase;
-  }
+  /* Make sure all SPICE file reading is case insensitive */
+  matchfunc = matchnocase;
+  matchintfunc = matchfilenocase;
+  hashfunc = hashnocase;
 
   InitializeHashTable(&spiceparams, OBJHASHSIZE);
 
@@ -1996,18 +1980,14 @@ void IncludeSpice(char *fname, int parent, struct cellstack **CellStackPtr,
 	/* helps, if the file didn't have an extension.  But	*/
 	/* really, we're getting desperate at this point.	*/
 
-	if (strrchr(fname, '.') == NULL) {
+	if (strchr(fname, '.') == NULL) {
            SetExtension(name, fname, SPICE_EXTENSION);
            filenum = OpenParseFile(name, parent);
-	   if (filenum < 0) {
-             Fprintf(stderr, "Error in SPICE file include: No file %s\n", name);
-             return;
-	   }
-        }    
-        else {
-          Fprintf(stderr, "Error in SPICE file include: No file %s\n", fname);
-          return;
 	}
+        if (filenum < 0) {
+           Fprintf(stderr,"Error in SPICE file include: No file %s\n",name);
+           return;
+        }    
      }
   }
   ReadSpiceFile(fname, parent, CellStackPtr, blackbox);

base/verilog.c

@@ -98,31 +98,6 @@ struct bus *NewBus()
     return (wb);
 }
 
-//-------------------------------------------------------------------------
-// Find a character c in a string, assuming that string may contain
-// verilog names, where anything, including char c, may appear in the
-// string if it is a backslash-escaped name.  Only the position of
-// character c outside of a verilog name is reported.
-//-------------------------------------------------------------------------
-
-char *strvchr(char *string, char c)
-{
-    char *s;
-
-    for (s = string; *s != '\0'; s++) {
-	if (*s == '\\') {
-	    while (*s != '\0' && *s != ' ') s++;
-	    if (*s == '\0') {
-		Fprintf(stderr, "Error:  Verilog backslash-escaped name"
-			" does not end with a space.\n");
-		break;
-	    }
-	}
-	if (*s == c) return s;
-    }
-    return NULL;
-}
-
 //-------------------------------------------------------------------------
 // Get bus indexes from the notation name[a:b].  If there is only "name"
 // then look up the name in the bus hash list and return the index bounds.
@@ -308,7 +283,7 @@ int GetBusTok(struct bus *wb)
 
 int GetBus(char *astr, struct bus *wb)
 {
-    char *colonptr, *brackstart, *brackend, *sigend, sdelim, *aastr;
+    char *colonptr, *brackstart, *brackend, *sigend, sdelim;
     int result, start, end;
 
     if (wb == NULL) return 0;
@@ -327,8 +302,8 @@ int GetBus(char *astr, struct bus *wb)
 	astr++;
 	wb->end = 0;
 	while((*astr != '\0') && (*astr != '}')) {
-	    sigend = strvchr(astr, ',');
-	    if (sigend == NULL) sigend = strvchr(astr, '}');
+	    sigend = strchr(astr, ',');
+	    if (sigend == NULL) sigend = strchr(astr, '}');
 	    if (sigend == NULL) {
 		Printf("Badly formed wire bundle \"%s\"\n", astr - 1);
 		return 1;
@@ -350,22 +325,15 @@ int GetBus(char *astr, struct bus *wb)
 	return 0;
     }
 
-    // Delimiters may appear in backslash-escaped names. . . ignore these.
-    aastr = astr;
-    if (*aastr == '\\') {
-	aastr++;
-	while (*aastr != ' ' && *aastr != '\\' && *aastr != '\0') aastr++;
-    }
-
-    brackstart = strvchr(aastr, '[');
+    brackstart = strchr(astr, '[');
     if (brackstart != NULL) {
-	brackend = strvchr(aastr, ']');
+	brackend = strchr(astr, ']');
 	if (brackend == NULL) {
 	    Printf("Badly formed array notation \"%s\"\n", astr);
 	    return 1;
 	}
 	*brackend = '\0';
-	colonptr = strvchr(aastr, ':');
+	colonptr = strchr(astr, ':');
 	if (colonptr) *colonptr = '\0';
 	result = sscanf(brackstart + 1, "%d", &start);
 	if (colonptr) *colonptr = ':';
@@ -944,7 +912,7 @@ skip_endmodule:
     }
     else if (match(nexttok, "input") || match(nexttok, "output")
 		|| match(nexttok, "inout")) {
-	struct bus wb, *nb;
+	struct bus wb;
  
 	// Parsing of ports as statements not in the module pin list.
 	wb.start = wb.end = -1;
@@ -977,11 +945,6 @@ skip_endmodule:
 			    Port(portname);
 			}
 		    }
-		    /* Also register this port as a bus */
-		    nb = NewBus();
-		    nb->start = wb.start;
-		    nb->end = wb.end;
-		    HashPtrInstall(nexttok, nb, &buses);
 		    wb.start = wb.end = -1;
 		}
 		else {
@@ -1095,13 +1058,6 @@ skip_endmodule:
 	 kl->pdefault.ival = 1;
          kl->slop.ival = 0;
       }
-      else if (nexttok[0] == '(') {
-	 /* For now, the netgen verilog parser doesn't handle `define f(X) ... */
-	 SkipNewLine(VLOG_DELIMITERS);
-	 FREE(kl->key);
-	 FREE(kl);
-	 kl = NULL;
-      }
       else if (ConvertStringToInteger(nexttok, &ival) == 1) {
 	 /* Parameter parses as an integer */
       	 kl->type = PROP_INTEGER;
@@ -1115,19 +1071,12 @@ skip_endmodule:
          kl->slop.dval = 0.01;		// One percent default
       }
       else {
-         char *toks;
-
-	 /* Treat the parameter as a string; BUT pull everything to */
-	 /* EOL, not just the current token.			    */
-	 toks = GetLineAtTok();
-
+	 /* Treat the parameter as a string */
       	 kl->type = PROP_STRING;
-	 kl->pdefault.string = strsave(toks);
+	 kl->pdefault.string = strsave(nexttok);
          kl->slop.dval = 0.0;
-
-	 SkipNewLine(VLOG_DELIMITERS);
       }
-      if (kl) HashPtrInstall(kl->key, kl, &verilogdefs);
+      HashPtrInstall(kl->key, kl, &verilogdefs);
     }
     else if (match(nexttok, "`undef")) {
       struct property *kl = NULL;
@@ -1216,7 +1165,7 @@ skip_endmodule:
 	else {	    /* "assign" */
 	    SkipTokComments(VLOG_PIN_CHECK_DELIMITERS);
 	    if (GetBus(nexttok, &wb) == 0) {
-		char *aptr = strvchr(nexttok, '[');
+		char *aptr = strchr(nexttok, '[');
 		if (aptr != NULL) {
 		    *aptr = '\0';
 		    /* Find object of first net in bus */
@@ -1225,16 +1174,9 @@ skip_endmodule:
 		    lhs = LookupObject(nodename, CurrentCell);
 		    *aptr = '[';
 		}
-		else {
-		    strcpy(noderoot, nexttok);
-		    /* Set LHS to the start of the vector */
-		    sprintf(nodename, "%s[%d]", nexttok, wb.start);
-		    lhs = LookupObject(nodename, CurrentCell);
-		}
 	    }
 	    else {
 		lhs = LookupObject(nexttok, CurrentCell);
-		strcpy(noderoot, nexttok);
 	    }
 	    SkipTokComments(VLOG_DELIMITERS);
 	    if (lhs && ((!nexttok) || (!match(nexttok, "=")))) {
@@ -1277,7 +1219,7 @@ skip_endmodule:
 		}
 		else {
 		    if (GetBus(nexttok, &wb2) == 0) {
-			char *aptr = strvchr(nexttok, '[');
+			char *aptr = strchr(nexttok, '[');
 			j = wb2.start;
 			if (aptr != NULL) {
 			    *aptr = '\0';
@@ -1295,21 +1237,13 @@ skip_endmodule:
 			if (rhs != NULL) {
 			    Printf("Improper assignment;  left-hand side cannot "
 					"be parsed.\n");
-			    if (j != -1)
-			    	Printf("Right-hand side is \"%s\".\n", assignroot);
-			    else
-			    	Printf("Right-hand side is \"%s\".\n", rhs->name);
-			    Printf("Improper expression is \"%s\".\n", nexttok);
+			    Printf("Right-hand side is \"%s\".\n", rhs->name);
 			    break;
 			}
 			if (lhs != NULL) {
 			    Printf("Improper assignment;  right-hand side cannot "
 					"be parsed.\n");
-			    if (i != -1)
-			    	Printf("Left-hand side is \"%s\".\n", noderoot);
-			    else
-			    	Printf("Left-hand side is \"%s\".\n", lhs->name);
-			    Printf("Improper expression is \"%s\".\n", nexttok);
+			    Printf("Left-hand side is \"%s\".\n", lhs->name);
 			    /* Not parsable, probably behavioral verilog? */
 			    Printf("Module '%s' is not structural verilog, "
 				    "making black-box.\n", model);
@@ -1374,7 +1308,6 @@ skip_endmodule:
       struct portelement {
 	char *name;	// Name of port in subcell
 	char *net;	// Name of net connecting to port in the parent
-	int   width;	// Width of port, if port is a bus
 	struct portelement *next;
       };
 
@@ -1382,22 +1315,6 @@ skip_endmodule:
       struct objlist *obptr;
 
       strncpy(modulename, nexttok, 99);
-
-      /* If module name is a verilog primitive, then treat the module as a  */
-      /* black box (this is not a complete list.  Preferable to use hash    */
-      /* function instead of lots of strcmp() calls).			    */
-
-      if (!strcmp(modulename, "buf") || !strcmp(modulename, "notif1") ||
-	    !strcmp(modulename, "not") || !strcmp(modulename, "and") ||
-	    !strcmp(modulename, "or") || !strcmp(modulename, "bufif0") ||
-	    !strcmp(modulename, "bufif1") || !strcmp(modulename, "notif0")) {
-
-         Printf("Module contains verilog primitive '%s'.\n", nexttok);
-         Printf("Module '%s' is not structural verilog, making black-box.\n", model);
-	 SetClass(CLASS_MODULE);
-	 goto skip_endmodule;
-      }
-
       if (!(*CellStackPtr)) {
 	CellDef(fname, filenum);
 	PushStack(fname, CellStackPtr);
@@ -1500,7 +1417,6 @@ nextinst:
 	    else {
 	       new_port = (struct portelement *)CALLOC(1, sizeof(struct portelement));
 	       new_port->name = strsave(nexttok + 1);
-	       new_port->width = -1;
 	       SkipTokComments(VLOG_DELIMITERS);
 	       if (!match(nexttok, "(")) {
 	           Printf("Badly formed subcircuit pin line at \"%s\"\n", nexttok);
@@ -1522,25 +1438,25 @@ nextinst:
 	       }
 	       else {
 		  if (!strcmp(nexttok, "{")) {
-		     char *wire_bundle = (char *)MALLOC(1);
-		     char *new_wire_bundle = NULL;
-		     *wire_bundle = '\0';
-		     /* Wire bundle---read to "}" */
+		     char *in_line_net = (char *)MALLOC(1);
+		     char *new_in_line_net = NULL;
+		     *in_line_net = '\0';
+		     /* In-line array---read to "}" */
 		     while (nexttok) {
-			 new_wire_bundle = (char *)MALLOC(strlen(wire_bundle) +
+			 new_in_line_net = (char *)MALLOC(strlen(in_line_net) +
 				    strlen(nexttok) + 1);
 			 /* Roundabout way to do realloc() becase there is no REALLOC() */
-			 strcpy(new_wire_bundle, wire_bundle);
-			 strcat(new_wire_bundle, nexttok);
-			 FREE(wire_bundle);
-			 wire_bundle = new_wire_bundle;
+			 strcpy(new_in_line_net, in_line_net);
+			 strcat(new_in_line_net, nexttok);
+			 FREE(in_line_net);
+			 in_line_net = new_in_line_net;
 			 if (!strcmp(nexttok, "}")) break;
 			 SkipTokComments(VLOG_PIN_CHECK_DELIMITERS);
 		     }
 		     if (!nexttok) {
-			 Printf("Unterminated net in pin %s\n", wire_bundle);
+			 Printf("Unterminated net in pin %s\n", in_line_net);
 		     }
-		     new_port->net = wire_bundle;
+		     new_port->net = in_line_net;
 		  }
 		  else
 		     new_port->net = strsave(nexttok);
@@ -1642,40 +1558,19 @@ nextinst:
 	    // Check if net name is a wire bus or portion of a bus
 	    if (GetBus(scan->net, &wb) == 0) {
 		int range;
-
-		// This takes care of three situations:
-		// (1) The signal bus length matches the number of instances:
-		//     apply one signal per instance.
-		// (2) The signal bus length is a multiple of the number of instances:
-		//     apply a signal sub-bus to each instance.
-		// (3) The number of instances is a multiple of the signal bus length:
-		//     apply the same signal to each instance.
-
 		if ((arrayend - arraystart) == (wb.end - wb.start)) {
 		    // Net is a bus, but net is split over arrayed instances
 		    Port(scan->name);
 		}
 		else if (wb.start > wb.end) {
-		    if ((arraystart - arrayend) > (wb.start - wb.end))
-			range = (((arraystart - arrayend) + 1) /
-				    ((wb.start - wb.end) + 1)) - 1;
-		    else
-			range = (((wb.start - wb.end) + 1) /
-				    ((arraystart - arrayend) + 1)) - 1;
-
+		    range = wb.start - wb.end;
 		    for (i = range; i >= 0; i--) {
 			sprintf(defport, "%s[%d]", scan->name, i);
 			Port(defport);
 		    }
 		}
 		else {
-		    if ((arrayend - arraystart) >  (wb.end - wb.start))
-			range = (((arrayend - arraystart) + 1) /
-				    ((wb.end - wb.start) + 1)) - 1;
-		    else
-			range = (((wb.end - wb.start) + 1) /
-				    ((arrayend - arraystart) + 1)) - 1;
-
+		    range = wb.end - wb.start;
 		    for (i = 0; i <= range; i++) {
 			sprintf(defport, "%s[%d]", scan->name, i);
 			Port(defport);
@@ -1727,12 +1622,7 @@ nextinst:
 	    int j, result;
 	    struct objlist *bobj;
 	    char *bptr;
-	    int minnet, maxnet, testidx, width;
-
-	    width = portstart - portend;
-	    if (width < 0) width = -width;
-	    width++;
-	    scan->width = width;
+	    int minnet, maxnet, testidx;
 
 	    result = GetBus(scan->net, &wb);
 	    if (result == -1) {
@@ -1746,7 +1636,7 @@ nextinst:
 
 		for (bobj = CurrentCell->cell; bobj; bobj = bobj->next) {
 		    if (bobj->type == PORT) {
-			if ((bptr = strvchr(bobj->name, '[')) != NULL) {
+			if ((bptr = strchr(bobj->name, '[')) != NULL) {
 			    *bptr = '\0';
 			    if (!strcmp(bobj->name, scan->net)) {
 				*bptr = '[';
@@ -1758,7 +1648,7 @@ nextinst:
 			}
 		    }
 		    else if (bobj->type == NODE) {
-			if ((bptr = strvchr(bobj->name, '[')) != NULL) {
+			if ((bptr = strchr(bobj->name, '[')) != NULL) {
 			    *bptr = '\0';
 			    if (!strcmp(bobj->name, scan->net)) {
 				if (sscanf(bptr + 1, "%d", &testidx) == 1) {
@@ -1784,31 +1674,17 @@ nextinst:
 	    }
 
 	    if (result == 0) {
-	       int match = 0;
-	       int wblen, arraylen;
-
-	       arraylen = arraystart - arrayend;
-	       wblen = wb.start - wb.end;
-
-	       if (arraylen < 0) arraylen = -arraylen;
-	       if (wblen < 0) wblen = -wblen;
-
-	       arraylen++;
-	       wblen++;
-
-	       if ((scan->width * arraylen) == wblen) match = 1;
-	       else if (wblen == scan->width) match = 1;
-	       else if (wblen == arraylen) match = 1;
-	       else {
-		  Fprintf(stderr, "Warning:  Net %s bus width (%d) does not match "
-				"port %s bus width (%d) or array width (%d).\n",
-				scan->net, wblen, scan->name, scan->width, arraylen);
+	       if (((wb.start - wb.end) != (portstart - portend)) &&
+		   	((wb.start - wb.end) != (portend - portstart))) {
+		  if (((wb.start - wb.end) != (arraystart - arrayend)) &&
+			((wb.start - wb.end) != (arrayend - arraystart))) {
+		     Fprintf(stderr, "Error:  Net %s bus width does not match "
+				"port %s bus width.\n", scan->net, scan->name);
+		  }
+		  // Otherwise, net is bit-sliced across array of instances.
 	       }
-
-	       // Net is bit-sliced across array of instances.
-
-	       if (wb.start > wb.end) {
-		  char *bptr = NULL, *cptr = NULL, cchar, *netname;
+	       else if (wb.start > wb.end) {
+		  char *bptr, *cptr, cchar, *netname;
 		  unsigned char is_bundle = 0;
 		  struct bus wbb;
 
@@ -1819,8 +1695,8 @@ nextinst:
 		  if (*netname == '{') {
 		     is_bundle = 1;
 		     netname++;
-		     cptr = strvchr(netname, ',');
-		     if (cptr == NULL) cptr = strvchr(netname, '}');
+		     cptr = strchr(netname, ',');
+		     if (cptr == NULL) cptr = strchr(netname, '}');
 		     if (cptr == NULL) cptr = netname + strlen(netname) - 1;
 		     cchar = *cptr;
 		     *cptr = '\0';
@@ -1829,12 +1705,14 @@ nextinst:
 		  // Remove indexed part of scan->net
 		  if (GetBus(netname, &wbb) == 0) {
 		     i = wbb.start;
-		     if ((bptr = strvchr(netname, '[')) != NULL)
+		     if ((bptr = strchr(netname, '[')) != NULL)
 			 *bptr = '\0';
 		  }
 		  else
 		     i = -1;
 
+		  if (is_bundle) *cptr = cchar;	 /* Restore bundle delimiter */
+		  
 		  while (1) {
 	             new_port = (struct portelement *)CALLOC(1,
 				sizeof(struct portelement));
@@ -1845,7 +1723,6 @@ nextinst:
 		     else
 			 sprintf(vname, "%s[%d]", netname, i); 
 	             new_port->net = strsave(vname);
-		     new_port->width = scan->width;
 
 		     if (last == NULL)
 			head = new_port;
@@ -1859,36 +1736,34 @@ nextinst:
 
 		     if (portstart > portend) j--;
 		     else j++;
-		     if (i != -1) {
-			if (wbb.start > wbb.end) i--;
-			else i++;
-		     }
+		     if (wbb.start > wbb.end) i--;
+		     else i++;
 
 		     if (is_bundle &&
 			    ((i == -1) ||
 			    ((wbb.start > wbb.end) && (i < wbb.end)) ||
-			    ((wbb.start <= wbb.end) && (i > wbb.end)))) {
+			    ((wbb.start < wbb.end) && (i > wbb.end)))) {
 		         if (bptr) *bptr = '[';
 
 			 netname = cptr + 1;
-			 if (cptr) *cptr = cchar; /* Restore previous bundle delimiter */
-		         cptr = strvchr(netname, ',');
-			 if (cptr == NULL) cptr = strvchr(netname, '}');
+		         cptr = strchr(netname, ',');
+			 if (cptr == NULL) cptr = strchr(netname, '}');
 			 if (cptr == NULL) cptr = netname + strlen(netname) - 1;
 			 cchar = *cptr;
 			 *cptr = '\0';
 
 			 if (GetBus(netname, &wbb) == 0) {
 			    i = wbb.start;
-			    if ((bptr = strvchr(netname, '[')) != NULL)
+			    if ((bptr = strchr(netname, '[')) != NULL)
 				*bptr = '\0';
 			 }
 			 else i = -1;
+
+			 *cptr = cchar;	    /* Restore delimiter */
 		     }
 		  }
 		  FREE(scan);
 		  scan = last;
-		  if (cptr) *cptr = cchar; /* Restore bundle delimiter */
 	       }
 	    }
 	    else if (portstart != portend) {
@@ -1918,7 +1793,7 @@ nextinst:
          obptr = LookupInstance(locinst, CurrentCell);
          if (obptr != NULL) {
             do {
-	       struct bus wb, wb2;
+	       struct bus wb;
 	       char *obpinname;
 	       int obpinidx;
 
@@ -1940,19 +1815,14 @@ nextinst:
 		  scan = scan->next;
 	       }
 	       if (scan == NULL) {
-		  char localnet[100];
-
-		  /* Assume an implicit unconnected pin */
-		  sprintf(localnet, "_noconnect_%d_", localcount++);
-		  Node(localnet);
-		  join(localnet, obptr->name);
-		  Fprintf(stderr, "Note:  Implicit pin %s\n", obpinname);
+		  Fprintf(stderr, "Error:  No match in call for pin %s\n", obpinname);
+		  break;
 	       }
-	       else if (GetBus(scan->net, &wb) == 0) {
-		   char *bptr2;
+
+	       if (GetBus(scan->net, &wb) == 0) {
 		   char *scanroot;
 		   scanroot = strsave(scan->net);
-		   brackptr = strvchr(scanroot, '[');
+		   brackptr = strchr(scanroot, '[');
 		   if (brackptr) *brackptr = '\0';
 
 		   if (arraystart == -1) {
@@ -1984,37 +1854,16 @@ nextinst:
 		   else {
 		       // Instance must be an array
 		       char netname[128];
-		       int slice, portlen, siglen;
-
-		       /* Get the array size of the port for bit slicing */
-		       portlen = (scan->width < 0) ? 1 : scan->width;
-
-		       /* Get the full array size of the connecting bus */
-		       GetBus(scanroot, &wb2);
-		       siglen = wb2.start - wb2.end;
-		       if (siglen < 0) siglen = -siglen;
-		       siglen++;
-
-		       // If signal array is smaller than the portlength *
-		       // length of instance array, then the signal wraps.
-
-		       if (wb2.start >= wb2.end && arraystart >= arrayend) {
-			   slice = wb.start - (arraystart - i) * portlen;
-			   while (slice < wb2.end) slice += siglen;
-		       }
-		       else if (wb2.start < wb2.end && arraystart > arrayend) {
-			   slice = wb.start + (arraystart - i) * portlen;
-			   while (slice > wb2.end) slice -= siglen;
-		       }
-		       else if (wb2.start > wb2.end && arraystart < arrayend) {
-			   slice = wb.start - (arraystart + i) * portlen;
-			   while (slice < wb2.end) slice += siglen;
-		       }
-		       else { // (wb2.start < wb2.end && arraystart < arrayend)
-			   slice = wb.start + (arraystart + i) * portlen;
-			   while (slice > wb2.end) slice -= siglen;
-		       }
-
+		       int slice;
+		       if (wb.start >= wb.end && arraystart >= arrayend)
+			   slice = wb.start - (arraystart - i);
+		       else if (wb.start < wb.end && arraystart > arrayend)
+			   slice = wb.start + (arraystart - i);
+		       else if (wb.start > wb.end && arraystart < arrayend)
+			   slice = wb.start - (arraystart + i);
+		       else // (wb.start < wb.end && arraystart < arrayend)
+			   slice = wb.start + (arraystart + i);
+			   
 		       sprintf(netname, "%s[%d]", scanroot, slice);
 	               if (LookupObject(netname, CurrentCell) == NULL) Node(netname);
 	               join(netname, obptr->name);
@@ -2082,21 +1931,14 @@ char *ReadVerilogTop(char *fname, int *fnum, int blackbox)
   CurrentCell = NULL;
 
   if ((filenum = OpenParseFile(fname, *fnum)) < 0) {
+    char name[100];
 
-    if (strchr(fname, '.') == NULL) {
-      char name[1024];
-      SetExtension(name, fname, VERILOG_EXTENSION);
-      if ((filenum = OpenParseFile(name, *fnum)) < 0) {
-        Fprintf(stderr, "Error in Verilog file read: No file %s\n", name);
-        *fnum = filenum;
-        return NULL;
-      }
+    SetExtension(name, fname, VERILOG_EXTENSION);
+    if ((filenum = OpenParseFile(name, *fnum)) < 0) {
+      Fprintf(stderr,"Error in Verilog file read: No file %s\n",name);
+      *fnum = filenum;
+      return NULL;
     }    
-    else {
-       Fprintf(stderr, "Error in Verilog file read: No file %s\n", fname);
-       *fnum = filenum;
-       return NULL;
-    }
   }
 
   /* All Verilog file reading is case sensitive.  However:  if	*/
@@ -2107,11 +1949,6 @@ char *ReadVerilogTop(char *fname, int *fnum, int blackbox)
      Printf("Warning:  A case-insensitive file has been read and so the	"
 		"verilog file must be treated case-insensitive to match.\n");
   }
-  else {
-     matchfunc = match;
-     matchintfunc = matchfile;
-     hashfunc = hash;
-  }
 
   InitializeHashTable(&verilogparams, OBJHASHSIZE);
   InitializeHashTable(&verilogdefs, OBJHASHSIZE);
@@ -2199,15 +2036,11 @@ void IncludeVerilog(char *fname, int parent, struct cellstack **CellStackPtr,
 	if (strchr(fname, '.') == NULL) {
            SetExtension(name, fname, VERILOG_EXTENSION);
            filenum = OpenParseFile(name, parent);
-	   if (filenum < 0) {
-	      fprintf(stderr,"Error in Verilog file include: No file %s\n", name);
-	      return;
-	   }
         }
-	else {
+	if (filenum < 0) {
 	   fprintf(stderr,"Error in Verilog file include: No file %s\n", fname);
 	   return;
-        }
+        }    
      }
   }
   ReadVerilogFile(fname, parent, CellStackPtr, blackbox);

configure

@@ -4,6 +4,4 @@
 # all of its config scripts in a different directory than the configure
 # script itself.
 
-export CFLAGS="$CFLAGS -g"
-cd scripts
-exec ./configure "$@"
+( CFLAGS="-g" ; export CFLAGS ; cd scripts ; ./configure "$@" )

tcltk/Makefile

@@ -25,7 +25,7 @@ install-tcl: netgenexec${EXEEXT} $(DESTDIR)${INSTALL_BINDIR}/netgen.sh ${TCL_FIL
 netgenexec${EXEEXT}: netgenexec.c
 	${CC} ${CFLAGS} ${CPPFLAGS} ${DFLAGS_NOSTUB} netgenexec.c \
 		-o netgenexec${EXEEXT} \
-		${LIB_SPECS_NOSTUB} ${LDFLAGS} ${LIBS} ${GR_LIBS}
+		${LDFLAGS} ${LIBS} ${LIB_SPECS_NOSTUB}
 
 netgen.tcl: netgen.tcl.in
 	sed -e 's%TCL_DIR%${TCLDIR}%g' \

tcltk/netgen.sh

@@ -1,60 +0,0 @@
-#!/bin/bash
-#
-# For installation, put this file (netgen.sh) in a standard executable path.
-# Put startup script "netgen.tcl" and shared library "tclnetgen.so"
-# in ${CAD_ROOT}/netgen/tcl/, with a symbolic link from file
-# ".wishrc" to "netgen.tcl".
-#
-# This script starts irsim under the Tcl interpreter,
-# reading commands from a special .wishrc script which
-# launches irsim and retains the Tcl interactive interpreter.
-
-# Parse for the argument "-c[onsole]".  If it exists, run netgen
-# with the TkCon console.  Strip this argument from the argument list.
-
-TKCON=true
-BATCH=
-GUI=
-NETGEN_WISH=/usr/bin/wish
-export NETGEN_WISH
-
-# Hacks for Cygwin
-if [ ${TERM:=""} = "cygwin" ]; then
-   export PATH="$PATH:/usr/lib"
-   export DISPLAY=${DISPLAY:=":0"}
-fi
-
-# Preserve quotes in arguments (thanks, Stackoverflow!)
-arglist=''
-for i in "$@" ; do
-   case $i in
-      -noc*) TKCON=;;
-      -bat*) BATCH=true; TKCON=;;
-      -gui) GUI=true; TKCON=;;
-      *) arglist="$arglist${arglist:+ }\"${i//\"/\\\"}\"";;
-   esac
-done 
-
-if [ $TKCON ]; then
-
-   exec /usr/local/lib/netgen/tcl/tkcon.tcl \
-	-eval "source /usr/local/lib/netgen/tcl/console.tcl" \
-	-slave "package require Tk; set argc $#; set argv [list $arglist]; \
-	source /usr/local/lib/netgen/tcl/netgen.tcl"
-
-# Run the Python LVS manager GUI
-
-elif [ $GUI ]; then
-    exec /usr/local/lib/netgen/python/lvs_manager.py $@
-
-#
-# Run the stand-in for wish (netgenexec), which acts exactly like "wish"
-# except that it replaces ~/.wishrc with netgen.tcl.  This executable is
-# *only* needed when running without the console; the console itself is
-# capable of sourcing the startup script.
-#
-
-else
-   exec /usr/local/lib/netgen/tcl/netgenexec -- "$@"
-
-fi

tcltk/netgen.tcl

@@ -1,753 +0,0 @@
-# Wishrc startup for ToolScript (netgen)
-#
-# For installation:  Put this file and also tclnetgen.so into
-# directory ${CAD_ROOT}/netgen/tcl/, and set the "load" line below
-# to point to the location of tclnetgen.so.  Also see comments
-# in shell script "netgen.sh".
-#
-
-# Check namespaces for existence of other applications
-set UsingMagic 0
-set UsingXCircuit 0
-set UsingIRSIM 0
-set batchmode 0
-set nlist [namespace children]
-foreach i $nlist {
-   switch $i {
-      ::magic { set UsingMagic 1 }
-      ::xcircuit { set UsingXCircuit 1 }
-      ::irsim { set UsingIRSIM 1 }
-   }
-}
-
-# -lazy option not needed if stubs libraries are handled correctly
-# load -lazy /usr/local/lib/netgen/tcl/tclnetgen.so
-
-load /usr/local/lib/netgen/tcl/tclnetgen.so
-
-#----------------------------------------------------------------
-# Convert LVS list result into a JSON file 
-#----------------------------------------------------------------
-
-proc netgen::convert_to_json {filename lvs_final} {
-   set pidx [string last . $filename]
-   set jsonname [string replace $filename $pidx end ".json"]
-   if {![catch {open $jsonname w} fjson]} {
-      puts $fjson "\["
-      # Outer list is of each cell compared
-      set clen [llength $lvs_final]
-      set cidx 0
-      foreach circuit $lvs_final {
-         incr cidx
-         puts $fjson "  \{"
-         set nkeys [llength $circuit]
-         set kidx 0
-	 foreach {key value} $circuit {
-            incr kidx 2
-	    switch $key {
-	       name {
-	          puts $fjson "   \"${key}\": \["
-		  set cktval [lindex $value 0]
-		  puts $fjson "      \"${cktval}\","
-		  set cktval [lindex $value 1]
-		  puts $fjson "      \"${cktval}\""
-		  if {$kidx == $nkeys} {
-		     puts $fjson "   \]"
-		  } else {
-		     puts $fjson "   \],"
-		  }
-	       }
-	       pins {
-	          puts $fjson "   \"${key}\": \["
-	          puts $fjson "      \["
-		  set cktval [lindex $value 0]
-		  foreach pin [lrange $cktval 0 end-1] {
-		     puts $fjson "        \"$pin\","
-		  }
-		  set pin [lindex $cktval end]
-		  puts $fjson "        \"$pin\""
-	          puts $fjson "      \], \["
-		  set cktval [lindex $value 1]
-		  foreach pin [lrange $cktval 0 end-1] {
-		     puts $fjson "        \"$pin\","
-		  }
-		  set pin [lindex $cktval end]
-		  puts $fjson "        \"$pin\""
-	          puts $fjson "      \]"
-		  if {$kidx == $nkeys} {
-		     puts $fjson "   \]"
-		  } else {
-		     puts $fjson "   \],"
-		  }
-	       }
-               nets {
-	          puts $fjson "   \"${key}\": \["
-		  set cktval [lindex $value 0]
-		  puts $fjson "    $cktval,"
-		  set cktval [lindex $value 1]
-		  puts $fjson "    $cktval"
-		  if {$kidx == $nkeys} {
-		     puts $fjson "   \]"
-		  } else {
-		     puts $fjson "   \],"
-		  }
-               }
-	       devices {
-	          puts $fjson "   \"${key}\": \["
-	          puts $fjson "       \["
-		  set cktval [lindex $value 0]
-		  foreach dev [lrange $cktval 0 end-1] {
-		     set devname [lindex $dev 0]
-		     set devnum  [lindex $dev 1]
-		     puts $fjson "         \[\"${devname}\", ${devnum}\],"
-		  }
-		  set dev [lindex $cktval end]
-		  set devname [lindex $dev 0]
-		  set devnum  [lindex $dev 1]
-		  puts $fjson "         \[\"${devname}\", ${devnum} \]"
-	          puts $fjson "       \], \["
-		  set cktval [lindex $value 1]
-		  foreach dev [lrange $cktval 0 end-1] {
-		     set devname [lindex $dev 0]
-		     set devnum  [lindex $dev 1]
-		     puts $fjson "         \[\"${devname}\", ${devnum} \],"
-		  }
-		  set dev [lindex $cktval end]
-		  set devname [lindex $dev 0]
-		  set devnum  [lindex $dev 1]
-		  puts $fjson "         \[\"${devname}\", ${devnum} \]"
-	          puts $fjson "       \]"
-		  if {$kidx == $nkeys} {
-		     puts $fjson "   \]"
-		  } else {
-		     puts $fjson "   \],"
-		  }
-	       }
-	       goodnets -
-	       badnets {
-	          puts $fjson "   \"${key}\": \["
-		  set glen [llength $value]
-		  set gidx 0
-		  foreach group $value {
-		     incr gidx
-	             puts $fjson "      \["
-	             puts $fjson "        \["
-		     set cktval [lindex $group 0]
-		     set nlen [llength $cktval]
-		     set nidx 0
-		     foreach net $cktval {
-			incr nidx
-	                puts $fjson "          \["
-			set netname [string map {"\\" "\\\\"} [lindex $net 0]]
-		        puts $fjson "            \"$netname\","
-		        puts $fjson "            \["
-			set netconn [lindex $net 1]
-			foreach fanout [lrange $netconn 0 end-1] {
-			   set devname [lindex $fanout 0]
-			   set pinname [lindex $fanout 1]
-			   set count [lindex $fanout 2]
-			   if {$count == {}} {set count 0}
-		           puts $fjson "              \[ \"$devname\", \"$pinname\", $count \],"
-			}
-			set fanout [lindex $netconn end]
-			set devname [lindex $fanout 0]
-			set pinname [lindex $fanout 1]
-			set count [lindex $fanout 2]
-			if {$count == {}} {set count 0}
-		        puts $fjson "              \[ \"$devname\", \"$pinname\", $count \]"
-		        puts $fjson "            \]"
-			if {$nidx == $nlen} {
-	                   puts $fjson "          \]"
-			} else {
-	                   puts $fjson "          \],"
-			}
-		     }
-	             puts $fjson "        \], \["
-		     set cktval [lindex $group 1]
-		     set nlen [llength $cktval]
-		     set nidx 0
-		     foreach net $cktval {
-			incr nidx
-	                puts $fjson "          \["
-			set netname [string map {"\\" "\\\\"} [lindex $net 0]]
-		        puts $fjson "            \"$netname\","
-		        puts $fjson "            \["
-			set netconn [lindex $net 1]
-			foreach fanout [lrange $netconn 0 end-1] {
-			   set devname [lindex $fanout 0]
-			   set pinname [lindex $fanout 1]
-			   set count [lindex $fanout 2]
-			   if {$count == {}} {set count 0}
-		           puts $fjson "              \[ \"$devname\", \"$pinname\", $count \],"
-			}
-			set fanout [lindex $netconn end]
-			set devname [lindex $fanout 0]
-			set pinname [lindex $fanout 1]
-			set count [lindex $fanout 2]
-			if {$count == {}} {set count 0}
-		        puts $fjson "              \[ \"$devname\", \"$pinname\", $count \]"
-		        puts $fjson "            \]"
-			if {$nidx == $nlen} {
-	                   puts $fjson "          \]"
-			} else {
-	                   puts $fjson "          \],"
-			}
-		     }
-	             puts $fjson "        \]"
-		     if {$gidx == $glen} {
-	                puts $fjson "      \]"
-		     } else {
-	                puts $fjson "      \],"
-		     }
-		  }
-		  if {$kidx == $nkeys} {
-		     puts $fjson "   \]"
-		  } else {
-		     puts $fjson "   \],"
-		  }
-	       }
-	       goodelements -
-	       badelements {
-	          puts $fjson "   \"${key}\": \["
-		  set glen [llength $value]
-		  set gidx 0
-		  foreach group $value {
-		     incr gidx
-	             puts $fjson "      \["
-	             puts $fjson "        \["
-		     set cktval [lindex $group 0]
-		     set ilen [llength $cktval]
-		     set iidx 0
-		     foreach inst $cktval {
-			incr iidx
-	                puts $fjson "          \["
-			set instname [string map {"\\" "\\\\"} [lindex $inst 0]]
-		        puts $fjson "            \"$instname\","
-		        puts $fjson "            \["
-			set instpins [lindex $inst 1]
-			foreach fanout [lrange $instpins 0 end-1] {
-			   set pinname [lindex $fanout 0]
-			   set count [lindex $fanout 1]
-			   if {$count == {}} {set count 0}
-		           puts $fjson "              \[ \"$pinname\", $count \],"
-			}
-			set fanout [lindex $instpins end]
-			set pinname [lindex $fanout 0]
-			set count [lindex $fanout 1]
-			if {$count == {}} {set count 0}
-		        puts $fjson "              \[ \"$pinname\", $count \]"
-		        puts $fjson "            \]"
-			if {$iidx == $ilen} {
-	                   puts $fjson "          \]"
-			} else {
-	                   puts $fjson "          \],"
-			}
-		     }
-	             puts $fjson "        \], \["
-		     set cktval [lindex $group 1]
-		     set ilen [llength $cktval]
-		     set iidx 0
-		     foreach inst $cktval {
-			incr iidx
-	                puts $fjson "          \["
-			set instname [string map {"\\" "\\\\"} [lindex $inst 0]]
-		        puts $fjson "            \"$instname\","
-		        puts $fjson "            \["
-			set instpins [lindex $inst 1]
-			foreach fanout [lrange $instpins 0 end-1] {
-			   set pinname [lindex $fanout 0]
-			   set count [lindex $fanout 1]
-			   if {$count == {}} {set count 0}
-		           puts $fjson "              \[ \"$pinname\", $count \],"
-			}
-			set fanout [lindex $instpins end]
-			set pinname [lindex $fanout 0]
-			set count [lindex $fanout 1]
-			if {$count == {}} {set count 0}
-		        puts $fjson "              \[ \"$pinname\", $count \]"
-		        puts $fjson "            \]"
-			if {$iidx == $ilen} {
-	                   puts $fjson "          \]"
-			} else {
-	                   puts $fjson "          \],"
-			}
-		     }
-	             puts $fjson "        \]"
-		     if {$gidx == $glen} {
-	                puts $fjson "      \]"
-		     } else {
-	                puts $fjson "      \],"
-		     }
-		  }
-		  if {$kidx == $nkeys} {
-		     puts $fjson "   \]"
-		  } else {
-		     puts $fjson "   \],"
-		  }
-	       }
-	       properties {
-	          puts $fjson "   \"${key}\": \["
-		  set plen [llength $value]
-                  set pidx 0
-		  foreach instance $value {
-		     incr pidx
-	             puts $fjson "      \["
-		     set instnames [string map {"\\" "\\\\"} [lindex $instance 0]]
-		     set instname0 [string map {"\\" "\\\\"} [lindex $instnames 0]]
-	             puts $fjson "         \["
-		     puts $fjson "           \"${instname0}\","
-	             puts $fjson "           \["
-		     foreach property [lrange $instance 1 end-1] {
-		        set prop0 [lindex $property 0]
-			set propname [lindex $prop0 0]
-			set propval [lindex $prop0 1]
-		        puts $fjson "             \[\"${propname}\", \"${propval}\"\],"
-		     }
-		     set property [lindex $instance end]
-		     set prop0 [lindex $property 0]
-		     set propname [lindex $prop0 0]
-		     set propval [lindex $prop0 1]
-		     puts $fjson "             \[\"${propname}\", \"${propval}\"\]"
-	             puts $fjson "           \]"
-	             puts $fjson "         \],"
-		     set instname1 [string map {"\\" "\\\\"} [lindex $instnames 1]]
-	             puts $fjson "         \["
-		     puts $fjson "           \"${instname1}\","
-	             puts $fjson "           \["
-		     foreach property [lrange $instance 1 end-1] {
-		        set prop1 [lindex $property 1]
-			set propname [lindex $prop1 0]
-			set propval [lindex $prop1 1]
-		        puts $fjson "             \[\"${propname}\", \"${propval}\"\],"
-		     }
-		     set property [lindex $instance end]
-		     set prop1 [lindex $property 1]
-		     set propname [lindex $prop1 0]
-		     set propval [lindex $prop1 1]
-		     puts $fjson "             \[\"${propname}\", \"${propval}\"\]"
-	             puts $fjson "           \]"
-	             puts $fjson "         \]"
-		     if {$pidx == $plen} {
-	                puts $fjson "      \]"
-		     } else {
-	                puts $fjson "      \],"
-		     }
-		  }
-		  if {$kidx == $nkeys} {
-		     puts $fjson "   \]"
-		  } else {
-		     puts $fjson "   \],"
-		  }
-	       }
-	    }
-	 }
-         if {$cidx == $clen} {
-            puts $fjson "  \}"
-	 } else {
-            puts $fjson "  \},"
-	 }
-      }
-      puts $fjson "\]"
-   }
-   close $fjson
-}
-
-#----------------------------------------------------------------
-# Define the "lvs" command as a way of calling the netgen options
-# for standard compare, essentially the same as the old "netcomp"
-# standalone program.
-#
-# Use the "canonical" command to parse the file and cell names,
-# although if the cells have not been read in yet, then the
-# original syntax of filename or {filename cellname} is required.
-#
-# "args" is passed to verify and may therefore contain only the
-# value "-list" or nothing.  If "-list", then output is returned
-# as a nested list.
-#----------------------------------------------------------------
-
-proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
-   set dolist 0
-   set dojson 0
-   foreach arg $args {
-      if {$arg == "-list"} {
-	 puts stdout "Generating list result"
-	 set dolist 1
-	 set lvs_final {}
-      } elseif {$arg == "-json"} {
-	 puts stdout "Generating JSON file result"
-	 set dolist 1
-	 set dojson 1
-	 set lvs_final {}
-      } elseif {$arg == "-blackbox"} {
-	 puts stdout "Treating empty subcircuits as black-box cells"
-	 netgen::model blackbox on
-      } elseif {$arg == "-full"} {
-	 puts stdout "Using full symmetry breaking method"
-	 netgen::symmetry full
-      }
-   }
-
-   # Allow name1 or name2 to be a list of {filename cellname},
-   # A single <filename>, or any valid_cellname form if the
-   # file has already been read.
-
-   if {[catch {set flist1 [canonical $name1]}]} {
-      if {[llength $name1] == 2} {
-         set file1 [lindex $name1 0]
-         set cell1 [lindex $name1 1]
-      } else {
-         set file1 $name1
-         set cell1 $name1
-      }
-      puts stdout "Reading netlist file $file1"
-      set fnum1 [netgen::readnet $file1]
-   } else {
-      set cell1 [lindex $flist1 0]
-      set fnum1 [lindex $flist1 1]
-      set flist1 [canonical $fnum1]
-      set file1 [lindex $flist1 0]
-   }
-
-   if {[catch {set flist2 [canonical $name2]}]} {
-      if {[llength $name2] == 2} {
-         set file2 [lindex $name2 0]
-         set cell2 [lindex $name2 1]
-      } else {
-         set file2 $name2
-         set cell2 $name2
-      }
-      puts stdout "Reading netlist file $file2"
-      set fnum2 [netgen::readnet $file2]
-   } else {
-      set cell2 [lindex $flist2 0]
-      set fnum2 [lindex $flist2 1]
-      set flist2 [canonical $fnum2]
-      set file2 [lindex $flist2 0]
-   }
-
-   if {$fnum1 == $fnum2} {
-      puts stderr "Both cells are in the same netlist:  Cannot compare!"
-      return
-   }
-
-   set clist1 [cells list $fnum1]
-   set cidx [lsearch -regexp $clist1 ^$cell1$]
-   if {$cidx < 0} {
-      puts stderr "Cannot find cell $cell1 in file $file1"
-      return
-   } else {
-      set cell1 [lindex $clist1 $cidx]
-   }
-   set clist2 [cells list $fnum2]
-   set cidx [lsearch -regexp $clist2 ^$cell2$]
-   if {$cidx < 0} {
-      puts stderr "Cannot find cell $cell2 in file $file2"
-      return
-   } else {
-      set cell2 [lindex $clist2 $cidx]
-   }
-
-   netgen::compare assign "$fnum1 $cell1" "$fnum2 $cell2"
-
-   if {[file exists $setupfile]} {
-      puts stdout "Reading setup file $setupfile"
-      # Instead of sourcing the setup file, run each line so we can
-      # catch individual errors and not let them halt the LVS process
-      set perrors 0
-      if {![catch {open $setupfile r} fsetup]} {
-	 set sline 0
-	 set command {}
-	 while {[gets $fsetup line] >= 0} {
-	    incr sline
-	    append command $line "\n"
-	    if {[info complete $command]} {
-	       if {[catch {uplevel 1 [list namespace eval netgen $command]} msg]} {
-		  set msg [string trimright $msg "\n"]
-		  puts stderr "Error $setupfile:$sline (ignoring), $msg"
-		  incr perrors
-	       }
-	       set command {}
-	    }
-	 }
-	 close $fsetup
-      } else {
-	 puts stdout "Error:  Cannot read the setup file $setupfile"
-      }
-	
-      if {$perrors > 0} {
-	 puts stdout "Warning:  There were errors reading the setup file"
-      }
-   } elseif {[string first nosetup $setupfile] < 0} {
-      netgen::permute default	;# transistors and resistors
-      netgen::property default
-   }
-
-   if {[string first nolog $logfile] < 0} {
-      puts stdout "Comparison output logged to file $logfile"
-      netgen::log file $logfile
-
-      netgen::log start
-      netgen::log echo off
-      set dolog true
-   } else {
-      set dolog false
-   }
-
-   if {$dolist == 1} {
-      set endval [netgen::compare -list hierarchical "$fnum1 $cell1" "$fnum2 $cell2"]
-   } else {
-      set endval [netgen::compare hierarchical "$fnum1 $cell1" "$fnum2 $cell2"]
-   }
-   if {$endval == {}} {
-      netgen::log put "No cells in queue!\n"
-      return
-   }
-   set properr {}
-   set pinsgood 0
-   while {$endval != {}} {
-      if {$dolist == 1} {
-         netgen::run -list converge
-      } else {
-         netgen::run converge
-      }
-      netgen::log echo on
-      if {[verify equivalent]} {
-	 # Resolve automorphisms by pin and property
-	 if {$dolist == 1} {
-            netgen::run -list resolve
-	 } else {
-            netgen::run resolve
-	 }
-	 set uresult [verify unique]
-         if {$uresult == 0} {
-	    netgen::log put "   Networks match locally but not globally.\n"
-	    netgen::log put "   Probably connections are swapped.\n"
-	    netgen::log put "   Check the end of logfile ${logfile} for implicated nodes.\n"
-	    if {$dolist == 1} {
-	       verify -list nodes
-	    } else {
-	       verify nodes
-	    }
-
-	    # Flatten the non-matching subcircuit (but not the top-level cells)
-            if {[netgen::print queue] != {}} {
-	       netgen::log put "  Flattening non-matched subcircuits $endval"
-	       netgen::flatten class "[lindex $endval 0] $fnum1"
-	       netgen::flatten class "[lindex $endval 1] $fnum2"
-	    }
-	 } else {
-	    # Match pins
-            netgen::log echo off
-	    if {$dolist == 1} {
-		set result [equate -list pins "$fnum1 [lindex $endval 0]" \
-				"$fnum2 [lindex $endval 1]"]
-	    } else {
-		set result [equate pins "$fnum1 [lindex $endval 0]" \
-				"$fnum2 [lindex $endval 1]"]
-	    }
-	    if {$result != 0} {
-		equate classes "$fnum1 [lindex $endval 0]" \
-			 "$fnum2 [lindex $endval 1]"
-	    }
-	    set pinsgood $result
-            netgen::log echo on
-	 }
-	 if {$uresult == 2} {lappend properr [lindex $endval 0]}
-      } else {
-	 # Flatten the non-matching subcircuit (but not the top-level cells)
-         if {[netgen::print queue] != {}} {
-	    netgen::log put "  Flattening non-matched subcircuits $endval"
-	    netgen::flatten class "[lindex $endval 0] $fnum1"
-	    netgen::flatten class "[lindex $endval 1] $fnum2"
-	 }
-      }
-      netgen::log echo off
-      if {$dolist == 1} {
-         catch {lappend lvs_final $lvs_out}
-         set lvs_out {}
-         set endval [netgen::compare -list hierarchical]
-      } else {
-         set endval [netgen::compare hierarchical]
-      }
-   }
-   netgen::log echo off
-   puts stdout "Result: " nonewline
-   netgen::log echo on
-   if {$pinsgood == 0} {
-      netgen::log put "The top level cell failed pin matching.\n"
-   } else {
-      verify only
-   }
-   if {$properr != {}} {
-      netgen::log put "The following cells had property errors: $properr\n"
-   }
-   if {$dolog} {
-      netgen::log end
-   }
-   puts stdout "LVS Done."
-   if {$dojson == 1} {
-      netgen::convert_to_json $logfile $lvs_final
-   } elseif {$dolist == 1} {
-      return $lvs_final
-   }
-}
-
-# It is important to make sure no netgen commands overlap with Tcl built-in
-# commands, because otherwise the namespace import will fail.
-
-proc pushnamespace { name } {
-
-   set y [namespace eval ${name} info commands ::${name}::*]
-   set z [info commands]
-
-   foreach v $y {
-      regsub -all {\*} $v {\\*} i
-      set x [namespace tail $i]
-      if {[lsearch $z $x] < 0} {
-         namespace import $i
-      } else {
-            puts "Warning: ${name} command '$x' use fully-qualified name '$v'"
-      }
-   }
-}
-
-proc popnamespace { name } {
-   set z [info commands]
-   set l [expr [string length ${name}] + 5]
-
-   while {[set v [lsearch $z ${name}_tcl_*]] >= 0} {
-      set y [lindex $z $v]
-      set w [string range $y $l end]
-      interp alias {} ::$w {}
-      rename ::$y ::$w
-      puts "Info: replacing ::$w with ::$y"
-   }
-   namespace forget ::${name}::*
-}
-
-set auto_noexec 1       ;# don't EVER call UNIX commands w/o "shell" in front
-
-#----------------------------------------------------------------------
-# Cross-Application section
-#----------------------------------------------------------------------
-
-# Setup IRSIM assuming that the Tcl version is installed.
-# We do not need to rename procedure irsim to NULL because it is
-# redefined in a script, which simply overwrites the original.
-
-proc irsim { args } {
-   global CAD_ROOT
-   set irsimscript [glob -nocomplain ${CAD_ROOT}/irsim/tcl/irsim.tcl]
-   if { ${irsimscript} == {} } {
-      puts stderr "\"irsim\" requires Tcl-based IRSIM version 9.6 or newer."
-      puts stderr "Could not find script \"irsim.tcl\".  If IRSIM is installed in a"
-      puts stderr "place other than CAD_ROOT (=${CAD_ROOT}), use the command"
-      puts stderr "\"source <path>/irsim.tcl\" before doing \"irsim\"."
-   } else {
-      source $irsimscript
-      eval {irsim} $args
-   }
-}
-
-# Setup Xcircuit assuming that the Tcl version is installed.
-
-proc xcircuit { args } {
-   global CAD_ROOT
-   global argc
-   global argv
-   set xcircscript [glob -nocomplain ${CAD_ROOT}/xcircuit*/xcircuit.tcl]
-   if { ${xcircscript} == {} } {
-      puts stderr "\"xcircuit\" requires Tcl-based XCircuit version 3.1 or newer."
-      puts stderr "Could not find script \"xcircuit.tcl\".  If XCircuit is installed in a"
-      puts stderr "place other than CAD_ROOT (=${CAD_ROOT}), use the command"
-      puts stderr "\"source <path>/xcircuit.tcl\"."
-   } else {
-      # if there are multiple installed versions, choose the highest version.
-      if {[llength $xcircscript] > 1} {
-        set xcircscript [lindex [lsort -decreasing -dictionary $xcircscript] 0]
-      }
-      set argv $args
-      set argc [llength $args]
-      uplevel #0 source $xcircscript
-   }
-}
-
-# Setup Magic assuming that the Tcl version is installed.
-
-proc magic { args } {
-   global CAD_ROOT
-   global argc
-   global argv
-   set magicscript [glob -nocomplain ${CAD_ROOT}/magic/tcl/magic.tcl]
-   if { ${magicscript} == {} } {
-      puts stderr "\"magic\" requires Tcl-based Magic version 7.2 or newer."
-      puts stderr "Could not find script \"magic.tcl\".  If Magic is installed in a"
-      puts stderr "place other than CAD_ROOT (=${CAD_ROOT}), use the command"
-      puts stderr "\"source <path>/magic.tcl\"."
-   } else {
-      set argv $args
-      set argc [llength $args]
-      uplevel #0 source $magicscript
-   }
-}
-
-#----------------------------------------------------------------------------
-# Have we called netgen from tkcon or a clone thereof?  If so, set NetgenConsole
-#----------------------------------------------------------------------------
-
-if {! $UsingMagic } {
-   if {[lsearch [interp aliases] tkcon] != -1} {
-      set NetgenConsole tkcon
-      wm withdraw .
-   }
-}
-
-pushnamespace netgen
-
-#----------------------------------------------------------------------------
-# For now, if we are standalone, pop down the default Tk window.
-# Sometime later we may wish to provide a standalone GUI frontend in Tk
-# to improve upon the original X11 "xnetgen" frontend.  If so, its
-# definitions would go below.
-
-if {! $UsingMagic } {
-   if {[lsearch [interp aliases] tkcon] != -1} {
-      if {[string range [wm title .] 0 3] == "wish"} {
-	 wm withdraw .
-      }
-   }
-}
-
-#----------------------------------------------------------------------------
-# No-console mode drops "--" in front of the argument list and "-noc"
-# is retained, so remove them.  Internally, the console will be determined
-# by checking for a slave interpreter, so there is no need for any
-# action here other than removing the argument.
-
-if {[lindex $argv 0] == "--"} {
-   incr argc -1
-   set argv [lrange $argv 1 end]
-}
-
-if {[string range [lindex $argv 0] 0 3] == "-noc"} {
-   incr argc -1
-   set argv [lrange $argv 1 end]
-}
-
-if {[string range [lindex $argv 0] 0 3] == "-bat"} {
-   incr argc -1
-   set argv [lrange $argv 1 end]
-   set batchmode 1
-}
-
-#----------------------------------------------------------------------------
-# Anything on the command line is assumed to be a netgen command to evaluate
-
-if {[catch {eval $argv}]} {
-   puts stdout "$errorInfo"
-}
-if {$batchmode == 1} {quit}
-
-#----------------------------------------------------------------------------
-# Netgen start function drops back to interpreter after initialization & setup

tcltk/netgen.tcl.in

@@ -382,9 +382,6 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
       } elseif {$arg == "-blackbox"} {
 	 puts stdout "Treating empty subcircuits as black-box cells"
 	 netgen::model blackbox on
-      } elseif {$arg == "-full"} {
-	 puts stdout "Using full symmetry breaking method"
-	 netgen::symmetry full
       }
    }
 
@@ -504,7 +501,6 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
       return
    }
    set properr {}
-   set pinsgood 0
    while {$endval != {}} {
       if {$dolist == 1} {
          netgen::run -list converge
@@ -550,7 +546,6 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
 		equate classes "$fnum1 [lindex $endval 0]" \
 			 "$fnum2 [lindex $endval 1]"
 	    }
-	    set pinsgood $result
             netgen::log echo on
 	 }
 	 if {$uresult == 2} {lappend properr [lindex $endval 0]}
@@ -574,11 +569,7 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
    netgen::log echo off
    puts stdout "Result: " nonewline
    netgen::log echo on
-   if {$pinsgood == 0} {
-      netgen::log put "The top level cell failed pin matching.\n"
-   } else {
-      verify only
-   }
+   verify only
    if {$properr != {}} {
       netgen::log put "The following cells had property errors: $properr\n"
    }

tcltk/tclnetgen.c

@@ -85,7 +85,6 @@ int _netcmp_compare(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_iterate(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_summary(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_print(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
-int _netcmp_format(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_run(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_verify(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_automorphs(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
@@ -94,7 +93,6 @@ int _netcmp_ignore(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_permute(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_property(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_exhaustive(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
-int _netcmp_symmetry(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_restart(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_global(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
 int _netcmp_convert(ClientData, Tcl_Interp *, int, Tcl_Obj *CONST objv[]);
@@ -201,9 +199,6 @@ Command netcmp_cmds[] = {
 	{"print",		_netcmp_print,
 		"\n   "
 		"print netcomp internal data structure"},
-	{"format",		_netcmp_format,
-		"<col1_width> <col2_width>\n   "
-		"set width of formatted output"},
 	{"run",			_netcmp_run,
 		"[converge|resolve]\n   "
 		"converge: run netcomp to completion (convergence)\n   "
@@ -245,9 +240,6 @@ Command netcmp_cmds[] = {
 	{"exhaustive",		_netcmp_exhaustive,
 		"\n   "
 		"toggle exhaustive subdivision"},
-	{"symmetry",		_netcmp_symmetry,
-		"[fast|full]\n   "
-		"apply method for symmetry breaking"},
 	{"restart",		_netcmp_restart,
 		"\n   "
 		"start over (reset data structures)"},
@@ -1536,24 +1528,23 @@ int
 _netgen_model(ClientData clientData,
     Tcl_Interp *interp, int objc, Tcl_Obj *CONST objv[])
 {
-   struct nlist *tp, *tp2;
+   struct nlist *tp;
    char *model, *retclass;
    unsigned char class;
    int fnum = -1;
-   int result, index, nports, nports2;
+   int result, index, nports;
 
    char *modelclasses[] = {
       "undefined", "nmos", "pmos", "pnp", "npn",
       "resistor", "capacitor", "diode",
       "inductor", "module", "blackbox", "xline",
-      "moscap", "mosfet", "bjt", "subcircuit", "copy",
-      NULL
+      "moscap", "mosfet", "bjt", "subcircuit", NULL
    };
    enum OptionIdx {
       UNDEF_IDX,  NMOS_IDX, PMOS_IDX, PNP_IDX, NPN_IDX,
       RES_IDX, CAP_IDX, DIODE_IDX, INDUCT_IDX,
       MODULE_IDX, BLACKBOX_IDX, XLINE_IDX, MOSCAP_IDX,
-      MOSFET_IDX, BJT_IDX, SUBCKT_IDX, COPY_IDX
+      MOSFET_IDX, BJT_IDX, SUBCKT_IDX
    };
 
    if (objc != 3 && objc != 2) {
@@ -1585,7 +1576,7 @@ _netgen_model(ClientData clientData,
 
    if (objc == 3) {
       model = Tcl_GetString(objv[2]);
-      nports = NumberOfPorts(model, fnum);
+      nports = NumberOfPorts(model);
 
       if (Tcl_GetIndexFromObj(interp, objv[2], (CONST84 char **)modelclasses,
 		"class", 0, &index) != TCL_OK) {
@@ -1649,40 +1640,6 @@ _netgen_model(ClientData clientData,
 	    break;
 	 case SUBCKT_IDX:
 	    class = CLASS_SUBCKT;
-	    break;
-	 case COPY_IDX:
-	    /* "copy" is not a class, but indicates that the cell,  */
-	    /* if undefined or a module, should have its class	    */
-	    /* taken from the other circuit, if that circuit has a  */
-	    /* cell of the same name.				    */
-	    if (Circuit1 == NULL || Circuit2 == NULL) {
-		Tcl_SetResult(interp, "Circuits have not been queued for comparison.",
-			NULL);
-		return TCL_ERROR;
-	    }
-	    if (tp == Circuit1) {
-		tp2 = LookupCellFile(tp->name, Circuit2->file);
-		nports2 = NumberOfPorts(tp2->name, Circuit2->file);
-	    }
-	    else if (tp == Circuit2) {
-		tp2 = LookupCellFile(tp->name, Circuit1->file);
-		nports2 = NumberOfPorts(tp2->name, Circuit1->file);
-	    }
-	    else {
-		Tcl_SetResult(interp, "The referenced netlist is not being compared.",
-			NULL);
-		return TCL_ERROR;
-	    }
-	    /* Should a non-matching number of ports be considered a fatal error? */
-	    // if (nports2 != nports) {
-	    //	Tcl_SetResult(interp, "The number of ports for this cell does not "
-	    //		"match between netlists.", NULL);
-	    //	return TCL_ERROR;
-	    // }
-
-	    class = tp2->class;
-	    /* To do (maybe): Rename tp ports to match tp2? */
-
 	    break;
       }
       tp->class = class;
@@ -2014,61 +1971,6 @@ _netgen_printmem(ClientData clientData,
 }
 #endif
 
-/*------------------------------------------------------*/
-/* Function name: _netcmp_format			*/
-/* Syntax:						*/
-/*    netgen::format [col1_width [col2_width]]		*/
-/* Formerly: (none)					*/
-/* Results:						*/
-/* Side Effects:					*/
-/*------------------------------------------------------*/
-
-int
-_netcmp_format(ClientData clientData,
-    Tcl_Interp *interp, int objc, Tcl_Obj *CONST objv[])
-{
-    int col1_width = 41, col2_width = 41;
-
-    if (objc > 1) {
-	if (Tcl_GetIntFromObj(interp, objv[1], &col1_width) != TCL_OK)
-	    return TCL_ERROR;
-	if (objc > 2) {
-	    if (Tcl_GetIntFromObj(interp, objv[2], &col2_width) != TCL_OK)
-		return TCL_ERROR;
-	} else {
-	    /* If only one argument is given, then apply it to both columns */
-	    col2_width = col1_width;
-	}
-
-	if (col1_width <= 0 || col2_width <= 0) {
-	    Tcl_SetResult(interp, "Column width cannot be zero or less\n", NULL);
-	}
-
-	// Default values for left and right columns are 43 and 87
-	left_col_end = col1_width + 2;
-	right_col_end = left_col_end + col2_width + 3;
-    }
-    else if (objc == 1) {
-	Tcl_Obj *lobj, *tobj;
-
-	col1_width = left_col_end - 2;
-	col2_width = right_col_end - col1_width - 5;
-
-	lobj = Tcl_NewListObj(0, NULL);
-
-	tobj = Tcl_NewIntObj(col1_width);
-        Tcl_ListObjAppendElement(interp, lobj, Tcl_NewIntObj(col1_width));
-        Tcl_ListObjAppendElement(interp, lobj, Tcl_NewIntObj(col2_width));
-
-	Tcl_SetObjResult(interp, lobj);
-	return TCL_OK;
-    }
-    else {
-	Tcl_WrongNumArgs(interp, 1, objv, "[col1_width [col2_width]]");
-	return TCL_ERROR;
-    }
-}
-
 /*------------------------------------------------------*/
 /* The following code breaks up the NETCOMP() command	*/
 /* from netcmp.c into individual functions w/arguments	*/
@@ -2998,34 +2900,15 @@ _netcmp_equate(ClientData clientData,
 
       case PINS_IDX:
 	 if ((ElementClasses == NULL) && (auto_blackbox == FALSE)) {
-	    if (CurrentCell == NULL) {
+	    if (CurrentCell == NULL)
 		Fprintf(stderr, "Equate elements:  no current cell.\n");
-		Tcl_SetObjResult(interp, Tcl_NewBooleanObj(0));
-		return TCL_OK;
-	    }
-	    else if ((tp1->flags & CELL_PLACEHOLDER) ||
-			(tp2->flags & CELL_PLACEHOLDER)) {
-		if (tp1->flags & CELL_PLACEHOLDER) {
-		    Fprintf(stdout, "Warning: Equate pins:  cell %s "
-			"has no definition, treated as a black box.\n", name1);
-		}
-		if (tp2->flags & CELL_PLACEHOLDER) {
-		    Fprintf(stdout, "Warning: Equate pins:  cell %s "
-			"has no definition, treated as a black box.\n", name2);
-		}
-		// If a cell in either circuit is marked as a black box, then
-		// the cells in both circuits should be marked as a black box.
-		tp1->flags |= CELL_PLACEHOLDER;
-		tp2->flags |= CELL_PLACEHOLDER;
-	    }
-	    else {
-		Fprintf(stdout, "Equate pins:  cell %s and/or %s "
-			"has no elements.\n", name1, name2);
-		/* This is not necessarily an error, so go ahead and match pins. */
-	    }
+	    Fprintf(stderr, "Equate pins:  cell %s and/or %s has no elements.\n",
+			name1, name2);
+	    Tcl_SetObjResult(interp, Tcl_NewBooleanObj(0));
+	    return TCL_OK;
 	 }
-	 if (ElementClasses == NULL) {
-	    /* This may have been called outside of a netlist compare,	*/
+	 else if (ElementClasses == NULL) {
+	    /* This has been called outside of a netlist compare,	*/
 	    /* probably to force name matching of pins on black-box	*/
 	    /* devices.  But MatchPins only works if tp1 == Circuit1	*/
 	    /* and tp2 == Circuit2, so preserve these values and 	*/
@@ -3976,48 +3859,6 @@ _netcmp_permute(ClientData clientData,
    return TCL_OK;
 }
 
-/*------------------------------------------------------*/
-/* Function name: _netcmp_symmetry			*/
-/* Syntax: netgen::symmetry [fast|full]			*/
-/* Formerly: x						*/
-/* Results:						*/
-/* Side Effects:					*/
-/*------------------------------------------------------*/
-
-int
-_netcmp_symmetry(ClientData clientData,
-    Tcl_Interp *interp, int objc, Tcl_Obj *CONST objv[])
-{
-   char *fastfull[] = {
-      "fast", "full", NULL
-   };
-   enum OptionIdx {
-      FAST_IDX, FULL_IDX
-   };
-   int result, index;
-
-   if (objc == 1)
-      index = -1;
-   else {
-      if (Tcl_GetIndexFromObj(interp, objv[1], (CONST84 char **)fastfull,
-		"option", 0, &index) != TCL_OK)
-         return TCL_ERROR;
-   }
-
-   switch(index) {
-      case FAST_IDX:
-	 FastSymmetryBreaking = TRUE;
-	 break;
-      case FULL_IDX:
-	 FastSymmetryBreaking = FALSE;
-	 break;
-   }
-   Printf("Symmetry breaking method: %s.\n", 
-	     FastSymmetryBreaking ? "FAST" : "FULL");
-
-   return TCL_OK;
-}
-
 /*------------------------------------------------------*/
 /* Function name: _netcmp_exhaustive			*/
 /* Syntax: netgen::exhaustive [on|off]			*/
@@ -4039,7 +3880,7 @@ _netcmp_exhaustive(ClientData clientData,
    int result, index;
 
    if (objc == 1)
-      index = -1;
+      index = YES_IDX;
    else {
       if (Tcl_GetIndexFromObj(interp, objv[1], (CONST84 char **)yesno,
 		"option", 0, &index) != TCL_OK)