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29 Commits
Author SHA1 Message Date
Tim Edwards 5cd68b9ef1 Merge branch 'master' into work 2017-06-18 22:48:13 -04:00
Tim Edwards 07788e7501 Update at Sun Jun 18 22:48:11 EDT 2017 by tim 2017-06-18 22:48:11 -04:00
Tim Edwards 24cc7d0c94 Update to add "property parallel none" command option. 2017-06-18 22:47:51 -04:00
Tim Edwards dbcd36d3ec Merge branch 'master' into work 2017-05-15 16:31:03 -04:00
Tim Edwards 25c17abb70 Update at Mon May 15 16:31:00 EDT 2017 by tim 2017-05-15 16:31:00 -04:00
Tim Edwards fd019b4afd Corrected the same error as a few commits back that causes a message
about property errors to show up, not due to property errors, but
due to proxy pins being inserted in the middle of a device record.
However, the first one was fixed for the case of proxy pins being
added to circuit 1, but the same fix was not made for the opposite
case of proxy pins being added to circuit 2.  This commit corrects
that omission.
2017-05-15 16:29:12 -04:00
Tim Edwards cdfd74bac4 Removed old comment from code referring to the development state. 2017-05-08 21:00:43 -04:00
Tim Edwards dd9e02c5f3 Merge branch 'master' into work 2017-05-08 20:57:01 -04:00
Tim Edwards 26cd16f3ff Update at Mon May 8 20:56:58 EDT 2017 by tim 2017-05-08 20:56:58 -04:00
Tim Edwards ccdd47bc0b Corrected rare case where a cell that is flattened is the first
instance in a cell, and is empty, and causes the cell contents
to be nulled out.
2017-05-08 20:55:58 -04:00
Tim Edwards ace1c28507 Corrected an error placing proxy pins after the first pin of the
first object if the (presumably top-level) cell has no pins
(top-level cells not in a subcircuit definition satisfy this
condition).
2017-05-05 21:08:09 -04:00
Tim Edwards 5e9635e05f Merge branch 'master' into work 2017-05-05 17:36:32 -04:00
Tim Edwards 5c168946e3 Update at Fri May 5 17:36:29 EDT 2017 by tim 2017-05-05 17:36:29 -04:00
Tim Edwards 1471f0c09f Corrected error in combining property records of serial devices. 2017-05-05 17:35:57 -04:00
Tim Edwards 73b81fcfe3 Merge branch 'master' into work 2017-04-25 08:47:58 -04:00
Tim Edwards b083a6df7c Update at Tue Apr 25 08:47:57 EDT 2017 by tim 2017-04-25 08:47:57 -04:00
Tim Edwards 2b5a96500c Corrected the .gitignore file, which was apparently missed when
version 1.5 was first created in git.
2017-04-25 08:47:33 -04:00
Tim Edwards 66f94b47e6 Merge branch 'master' into work 2017-03-06 14:01:26 -05:00
Tim Edwards 09532ee628 Update at Mon Mar 6 14:01:25 EST 2017 by tim 2017-03-06 14:01:25 -05:00
Tim Edwards 2b7d416a41 A few corrections to the JSON format output. 2017-03-06 14:01:14 -05:00
Tim Edwards 090e9e122a Merge branch 'master' into work 2017-03-03 09:11:54 -05:00
Tim Edwards 67f1c1a2e9 Update at Fri Mar 3 09:11:52 EST 2017 by tim 2017-03-03 09:11:52 -05:00
Tim Edwards a7dcb4ef45 Corrected new JSON file output format from netgen. 2017-03-03 09:11:30 -05:00
Tim Edwards a0f1b4cc92 Merge branch 'master' into work 2017-02-27 09:36:54 -05:00
Tim Edwards b5d5496e40 Update at Mon Feb 27 09:36:52 EST 2017 by tim 2017-02-27 09:36:52 -05:00
Tim Edwards 7cac67c81b Corrected an error in the property match subroutine that was failing
to stop at the end of an instance record without properties, leading
to strange errors where netgen declares "There were property errors"
but does not print any errors (because there aren't any).
2017-02-27 09:35:18 -05:00
Tim Edwards ede7406b08 Merge branch 'master' into work 2017-02-08 15:17:01 -05:00
Tim Edwards 516d1c33fb Update at Wed Feb 8 15:16:59 EST 2017 by tim 2017-02-08 15:16:59 -05:00
Tim Edwards 0ad5730701 Corrected an error where snprintf() was not used when printing
formatted side-by-side output, causing a crash for names that
exceed the 40-column limit.
2017-02-08 15:16:24 -05:00
9 changed files with 109 additions and 77 deletions
+11 -10
View File
@@ -1,12 +1,13 @@
*.*%
*.cdslck
.inca.db.*
inca.*.pak
*.swp
*.log
netgen
netgenexec
defs.mak
Depend
config.cache
config.log
config.status
*.o
*.so
*~
*/av_extracted*/
.nfs*
*.cd-
*/mommdl/
*.log
UPDATE_ME
VERSION
+6 -5
View File
@@ -1,15 +1,14 @@
TO_DO list for version 1.5
------------------------------
1) Parallel (transistors and capacitors) and serial (resistors)
device merging, plus methods for describing how any device
class may be merged.
As of version 1.5.70, the major to-do item list is complete.
Possible useful additions (not critical)
----------------------
1) Add new output style allowing netlists to be described by Tcl scripts
(similar to the C-Code format, but does not require compiling).
(similar to the C-Code format, but does not require compiling) (this
was done in 1.5.72, but now needs some scripts to make use of it.)
2) Add automatic file format guessing from file extension for "write" command
3) Add Tk GUI to match (and improve upon!) the original X11 GUI.
4) Incorporate into Tcl-based xcircuit
@@ -33,5 +32,7 @@ Possible useful additions (not critical)
ntk and ext formats, SPICE format writing, and sim format reading).
11) Add a "property" command to add/remove properties to check, and change
the slop values (done).
12) Add a "subcircuit" command to mimic a SPICE ".SUBCKT ... .ENDS" card.
12) Add a "subcircuit" command to mimic a SPICE ".SUBCKT ... .ENDS" card
(i.e., the ability to add subcircuit "stub" definitions from the
command line or from a setup file).
+1 -1
View File
@@ -1 +1 @@
1.5.71
1.5.80
+21 -15
View File
@@ -486,24 +486,30 @@ int flattenInstancesOf(char *name, int fnum, char *instance)
}
/* splice instance out of parent */
if (ParentParams == ThisCell->cell) {
/* ParentParams are the very first thing in the list */
ThisCell->cell = ChildObjList;
for (ob2 = ChildObjList; ob2 && ob2->next != NULL; ob2 = ob2->next) ;
if ((ParentParams == ThisCell->cell) && (ChildObjList == NULL)) {
ThisCell->cell = ob2; /* Child cell was empty */
tmp = ob2;
}
else {
/* find ParentParams in ThisCell list */
for (ob2 = ThisCell->cell; ob2 && ob2->next != ParentParams; ob2=ob2->next);
if (ob2)
for (ob2->next = ChildObjList; ob2->next != NULL; ob2 = ob2->next) ;
}
/* now, ob2 is last element in child list, so skip and reclaim parent */
if (ParentParams == ThisCell->cell) {
/* ParentParams are the very first thing in the list */
ThisCell->cell = ChildObjList;
for (ob2 = ChildObjList; ob2 && ob2->next != NULL; ob2 = ob2->next) ;
}
else {
/* find ParentParams in ThisCell list */
for (ob2 = ThisCell->cell; ob2 && ob2->next != ParentParams; ob2=ob2->next);
if (ob2)
for (ob2->next = ChildObjList; ob2->next != NULL; ob2 = ob2->next) ;
}
/* now, ob2 is last element in child list, so skip and reclaim parent */
tmp = ParentParams;
do {
tmp = tmp->next;
} while ((tmp != NULL) && ((tmp->type > FIRSTPIN) || (tmp->type == PROPERTY)));
if (ob2) ob2->next = tmp;
tmp = ParentParams;
do {
tmp = tmp->next;
} while ((tmp != NULL) && ((tmp->type > FIRSTPIN) || (tmp->type == PROPERTY)));
if (ob2) ob2->next = tmp;
}
while (ParentParams != tmp) {
ob2 = ParentParams->next;
FreeObjectAndHash(ParentParams, ThisCell);
+33 -18
View File
@@ -5002,10 +5002,12 @@ PropertyMatch(struct objlist *ob1, struct objlist *ob2, int do_print,
/* Find the first property record of each circuit. obn1, obn2 are */
/* the last device record before the properties for each device. */
for (tp1 = ob1; (tp1 != NULL) && tp1->type >= FIRSTPIN; tp1 = tp1->next)
for (tp1 = ob1->next; (tp1 != NULL) && tp1->type > FIRSTPIN; tp1 = tp1->next)
obn1 = tp1;
for (tp2 = ob2; (tp2 != NULL) && tp2->type >= FIRSTPIN; tp2 = tp2->next)
for (tp2 = ob2->next; (tp2 != NULL) && tp2->type > FIRSTPIN; tp2 = tp2->next)
obn2 = tp2;
if (tp1 && (tp1->type == FIRSTPIN)) tp1 = NULL; /* tp1 had no properties */
if (tp2 && (tp2->type == FIRSTPIN)) tp2 = NULL; /* tp2 had no properties */
/* Check if there are any properties to match */
@@ -5076,7 +5078,6 @@ PropertyMatch(struct objlist *ob1, struct objlist *ob2, int do_print,
// t1 has no properties. See if t2's properties are required
// to be checked. If so, flag t2 instance as unmatched
mismatches++;
for (i = 0;; i++) {
vl2 = &(tp2->instance.props[i]);
if (vl2->type == PROP_ENDLIST) break;
@@ -5086,6 +5087,7 @@ PropertyMatch(struct objlist *ob1, struct objlist *ob2, int do_print,
if (kl2 != NULL) break; // Property is required
}
if (vl2->type != PROP_ENDLIST) {
mismatches++;
if (do_print) Fprintf(stdout, "Circuit 2 %s instance %s has no"
" property match in circuit 1.\n",
Circuit2->name, inst2);
@@ -6373,11 +6375,11 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
if (Debug == 0) {
for (m = 0; m < 43; m++) *(ostr + m) = ' ';
for (m = 44; m < 87; m++) *(ostr + m) = ' ';
sprintf(ostr, "%s", obn->name);
snprintf(ostr, 43, "%s", obn->name);
if (!strcasecmp(obn->name, obp->name))
sprintf(ostr + 44, "%s", obp->name);
snprintf(ostr + 44, 43, "%s", obp->name);
else
sprintf(ostr + 44, "%s **Mismatch**", obp->name);
snprintf(ostr + 44, 43, "%s **Mismatch**", obp->name);
for (m = 0; m < 88; m++)
if (*(ostr + m) == '\0') *(ostr + m) = ' ';
Fprintf(stdout, ostr);
@@ -6411,8 +6413,8 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
if (strcmp(obn->name, "(no pins)")) {
for (m = 0; m < 43; m++) *(ostr + m) = ' ';
for (m = 44; m < 87; m++) *(ostr + m) = ' ';
sprintf(ostr, "%s", obn->name);
sprintf(ostr + 44, "(no matching pin)");
snprintf(ostr, 32, "%s", obn->name);
snprintf(ostr + 44, 43, "(no matching pin)");
for (m = 0; m < 88; m++)
if (*(ostr + m) == '\0') *(ostr + m) = ' ';
Fprintf(stdout, ostr);
@@ -6456,8 +6458,8 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
if (Debug == 0) {
for (m = 0; m < 43; m++) *(ostr + m) = ' ';
for (m = 44; m < 87; m++) *(ostr + m) = ' ';
sprintf(ostr, "%s", obn->name);
sprintf(ostr + 44, "(no matching pin)");
snprintf(ostr, 43, "%s", obn->name);
snprintf(ostr + 44, 43, "(no matching pin)");
for (m = 0; m < 88; m++)
if (*(ostr + m) == '\0') *(ostr + m) = ' ';
Fprintf(stdout, ostr);
@@ -6498,8 +6500,8 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
if (Debug == 0) {
for (m = 0; m < 43; m++) *(ostr + m) = ' ';
for (m = 44; m < 87; m++) *(ostr + m) = ' ';
sprintf(ostr, "%s", ob1->name);
sprintf(ostr + 44, "%s", ob2->name);
snprintf(ostr, 43, "%s", ob1->name);
snprintf(ostr + 44, 43, "%s", ob2->name);
for (m = 0; m < 88; m++)
if (*(ostr + m) == '\0') *(ostr + m) = ' ';
Fprintf(stdout, ostr);
@@ -6545,8 +6547,8 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
if (strcmp(ob2->name, "(no pins)")) {
for (m = 0; m < 43; m++) *(ostr + m) = ' ';
for (m = 44; m < 87; m++) *(ostr + m) = ' ';
sprintf(ostr, "(no matching pin)");
sprintf(ostr + 44, "%s", ob2->name);
snprintf(ostr, 43, "(no matching pin)");
snprintf(ostr + 44, 43, "%s", ob2->name);
for (m = 0; m < 88; m++)
if (*(ostr + m) == '\0') *(ostr + m) = ' ';
Fprintf(stdout, ostr);
@@ -6595,8 +6597,14 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
obn->model.port = -1;
obn->instance.name = NULL;
obn->node = -1;
obn->next = ob1->next;
ob1->next = obn;
if (ob1 == tc1->cell) {
obn->next = ob1;
tc1->cell = obn;
}
else {
obn->next = ob1->next;
ob1->next = obn;
}
ob1 = obn;
hasproxy1 = 1;
@@ -6653,8 +6661,15 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
obn->model.port = (i - j);
obn->instance.name = NULL;
obn->node = -1;
obn->next = ob2->next;
ob2->next = obn;
if (ob2 == tc2->cell) {
obn->next = ob2;
tc2->cell = obn;
}
else {
obn->next = ob2->next;
ob2->next = obn;
}
ob2 = obn;
hasproxy2 = 1;
+8 -12
View File
@@ -49,6 +49,7 @@ int NextNode;
int Composition = NONE;
int QuickSearch = 0;
int GlobalParallelNone = FALSE;
int AddToExistingDefinition = 0; /* default: overwrite cell when reopened */
@@ -1192,7 +1193,7 @@ void CellDef(char *name, int fnum)
np = InstallInCellHashTable(name, fnum);
CurrentCell = LookupCellFile(name, fnum);
CurrentCell->class = CLASS_SUBCKT; /* default */
CurrentCell->flags = 0;
CurrentCell->flags = (GlobalParallelNone) ? COMB_NO_PARALLEL : 0;
LastPlaced = NULL;
CurrentTail = NULL;
@@ -3306,11 +3307,6 @@ int CombineSerial(char *model, int file)
int i, j, scnt = 0;
struct valuelist *kv;
// To avoid posting a non-working version, serial combination is
// disabled here until code is finished to compare the serial/parallel
// property networks.
// return 0;
if ((tp = LookupCellFile(model, file)) == NULL) {
Printf("Cell: %s does not exist.\n", model);
return -1;
@@ -3387,11 +3383,10 @@ int CombineSerial(char *model, int file)
/* a parameter '_tag', string value set to "+". */
for (obn = instlist[i][1]; obn->next &&
obn->next->type != PROPERTY &&
obn->next->type != FIRSTPIN; obn = obn->next);
obn->next->type > FIRSTPIN; obn = obn->next);
obp = obn->next;
if (obp == NULL || obp->type == FIRSTPIN) {
if (obp == NULL || obp->type != PROPERTY) {
struct objlist *nob;
/* No property record, so insert one */
nob = GetObject();
@@ -3463,10 +3458,11 @@ int CombineSerial(char *model, int file)
/* Excise the 2nd instance. instlist[i][1] remains as the */
/* only pointer to it. */
for (obp = instlist[i][0]; obp->next->type != FIRSTPIN; obp = obp->next);
for (obp = instlist[i][0]; obp->next->type > FIRSTPIN ||
obp->next->type == PROPERTY; obp = obp->next);
for (ob2 = obp; ob2->next != instlist[i][1]; ob2 = ob2->next);
for (obs = ob2->next; obs->next && obs->next->type != FIRSTPIN;
obs = obs->next);
for (obs = ob2->next; obs->next && (obs->next->type > FIRSTPIN
|| obs->next->type == PROPERTY); obs = obs->next);
ob2->next = obs->next;
if (obs->next) obs->next = NULL; // Terminate 2nd instance record
+1
View File
@@ -132,6 +132,7 @@ extern int IgnoreRC; /* set this to 1 to ignore capacitance and resistance */
extern int NoOutput; /* set this to 1 to disable stdout output */
extern int Composition; /* direction of composition */
extern int UnixWildcards; /* TRUE if *,?,{},[] only; false if full REGEXP */
extern int GlobalParallelNone; /* If TRUE, don't parallel combine any cells */
/* magic internal flag to restrict searches to recently placed cells */
extern int QuickSearch;
/* does re"CellDef"ing a cell add to it or overwrite it??? */
+11 -15
View File
@@ -84,9 +84,9 @@ proc netgen::convert_to_json {filename lvs_final} {
nets {
puts $fjson " \"${key}\": \["
set cktval [lindex $value 0]
puts $fjson " \"$cktval\","
puts $fjson " $cktval,"
set cktval [lindex $value 1]
puts $fjson " \"$cktval\""
puts $fjson " $cktval"
if {$kidx == $nkeys} {
puts $fjson " \]"
} else {
@@ -194,15 +194,13 @@ proc netgen::convert_to_json {filename lvs_final} {
puts $fjson " \],"
}
}
puts $fjson " \]"
if {$gidx == $glen} {
puts $fjson " \]"
puts $fjson " \]"
} else {
puts $fjson " \],"
puts $fjson " \],"
}
}
if {$glen > 0} {
puts $fjson " \]"
}
if {$kidx == $nkeys} {
puts $fjson " \]"
} else {
@@ -275,15 +273,13 @@ proc netgen::convert_to_json {filename lvs_final} {
puts $fjson " \],"
}
}
puts $fjson " \]"
if {$gidx == $glen} {
puts $fjson " \]"
puts $fjson " \]"
} else {
puts $fjson " \],"
puts $fjson " \],"
}
}
if {$glen > 0} {
puts $fjson " \]"
}
if {$kidx == $nkeys} {
puts $fjson " \]"
} else {
@@ -326,9 +322,9 @@ proc netgen::convert_to_json {filename lvs_final} {
puts $fjson " \[\"${propname}\", \"${propval}\"\],"
}
set property [lindex $instance end]
set prop0 [lindex $property 0]
set propname [lindex $prop0 0]
set propval [lindex $prop0 1]
set prop1 [lindex $property 1]
set propname [lindex $prop1 0]
set propval [lindex $prop1 1]
puts $fjson " \[\"${propname}\", \"${propval}\"\]"
puts $fjson " \]"
puts $fjson " \]"
+17 -1
View File
@@ -3093,8 +3093,12 @@ _netcmp_equate(ClientData clientData,
/* netgen::property <device>|<model> <option> */
/* yes|no */
/* Where <option> is one of: */
/* serial --- allow/prohibit serial combination */
/* serial --- allow/prohibit serial combination */
/* parallel --- allow/prohibit parallel combination */
/* or */
/* netgen::property parallel none */
/* --- prohibit parallel combinations by */
/* default. */
/* */
/* Formerly: (none) */
/* Results: */
@@ -3188,6 +3192,18 @@ _netcmp_property(ClientData clientData,
}
return TCL_OK;
}
else if ((objc == 3) && (!strcmp(Tcl_GetString(objv[1]), "parallel"))) {
if (!strcmp(Tcl_GetString(objv[2]), "none"))
GlobalParallelNone = TRUE;
else if (!strcmp(Tcl_GetString(objv[2]), "all"))
GlobalParallelNone = FALSE;
else {
Tcl_SetResult(interp, "Bad option, should be property parallel none|all",
NONE);
return TCL_ERROR;
}
return TCL_OK;
}
result = CommonParseCell(interp, objv[1], &tp, &fnum);
if (result != TCL_OK) return result;