Merge branch 'master' into netgen-1.5

before its component cells, and the component cells are read in as
SPICE netlists.  Then the original verilog cell and its instances
need to have pins reordered to match the subcircuit definition in
the SPICE netlist.  Otherwise, when verilog and SPICE netlists are
mixed, the order in which the files are read is critical, and
failures due to reading out-of-order are very obscure and nearly
impossible to debug.

VERSION

@@ -1 +1 @@
-1.5.263
+1.5.267

base/netcmp.c

@@ -6124,7 +6124,9 @@ PropertyMatch(struct Element *E1, struct Element *E2,
 	    	if (kl2 != NULL)
 		    break;	// Property is required
 	    }
-	    else if (vl2->value.ival != 1)
+	    else if ((vl2->type == PROP_INTEGER) && (vl2->value.ival != 1))
+		break;	// Property M != 1 or S != 1 is a mismatch.
+	    else if ((vl2->type == PROP_DOUBLE) && (vl2->value.dval != 1))
 		break;	// Property M != 1 or S != 1 is a mismatch.
 	 }
 	 if (vl2->type != PROP_ENDLIST) {
@@ -7182,7 +7184,7 @@ int reorderpins(struct hashlist *p, int file)
 {
     struct nlist *ptr;
     struct nlist *tc2 = Circuit2;
-    struct objlist *ob, *ob2, *firstpin;
+    struct objlist *ob, *ob2, *firstpin, *oblast, *newob;
     int i, numports, *nodes, unordered;
     char **names;
 
@@ -7234,6 +7236,7 @@ int reorderpins(struct hashlist *p, int file)
 		        names[ob2->model.port] = ob->name;
 		    }
 
+		    oblast = ob;
 		    ob = ob->next;
 		    ob2 = ob2->next;
 		    if (i < numports - 1) {
@@ -7241,7 +7244,34 @@ int reorderpins(struct hashlist *p, int file)
 			    Fprintf(stderr, "Instance of %s has only "
 				"%d of %d ports\n",
 				tc2->name, i + 1, numports);
-			    break;
+		            if (ptr->flags & CELL_VERILOG) {
+			       /* If parent cell is verilog, and the cells
+			        * have been matched, then the instance can
+			        * be assumed to be using an implicit pin.
+			        */
+			       Fprintf(stderr, "Assuming implicit verilog pin \"%s\".\n",
+					ob2->name);
+		   	       newob = (struct objlist *)CALLOC(1,
+					sizeof(struct objlist));
+			       newob->name = (char *)MALLOC(strlen(oblast->instance.name)
+					+ strlen(ob2->name) + 2);
+			       sprintf(newob->name, "%s/%s",
+					oblast->instance.name, ob2->name);
+			       newob->type = oblast->type + 1;
+			       newob->model.class = strsave(oblast->model.class);
+			       newob->instance.name = strsave(oblast->instance.name);
+			       newob->flags = 0;
+			       ptr->nodename_cache_maxnodenum++;
+			       newob->node = ptr->nodename_cache_maxnodenum;
+			       newob->next = ob;
+			       oblast->next = newob;	/* Splice into object list */
+			       /* Fill in the missing entries */
+		               nodes[ob2->model.port] = newob->node;
+		 	       names[ob2->model.port] = newob->name;
+			       ob = newob;
+		            }
+			    else
+			       break;
 			}
 			else if (ob2 == NULL || ob2->type != PORT) {
 			    Fprintf(stderr, "Instance of %s has "
@@ -7443,6 +7473,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
    int hasproxy1 = 0, hasproxy2 = 0;
    int needclean1 = 0, needclean2 = 0;
    int nomatch = 0;
+   int filenum = -1;
    int *correspond;
    char *ostr;
 #ifdef TCL_NETGEN
@@ -8120,7 +8151,11 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
 
    /* Reorder pins in Circuit2 instances to match Circuit1 */
 
-   RecurseCellFileHashTable(reorderpins, Circuit2->file);
+   if (Circuit2 != NULL)
+      filenum = Circuit2->file;
+   else
+      filenum = tc2->file;
+   RecurseCellFileHashTable(reorderpins, filenum);
 
    /* Reorder pins in Circuit2 cell to match Circuit1		*/
    /* Unlike the instance records, the structures are swapped,	*/

base/netfile.c

@@ -587,6 +587,12 @@ void SkipTokNoNewline(char *delimiter)
 /*									*/
 /* Modified 3/30/2015 to include the condition where a comment line is	*/
 /* in the middle of a series of continuation lines.			*/
+/*									*/
+/* Modified 1/3/2024 to avoid skipping two lines if a line has only the	*/
+/* comment character '*' followed by a newline.  It seems that '\n' is	*/
+/* being ignored in WHITESPACE_DELIMITER, but it's easier to write the	*/
+/* code to find the exception rather than track down the problem in	*/
+/* GetNextLine().							*/
 /*----------------------------------------------------------------------*/
 
 void SpiceTokNoNewline(void)
@@ -598,8 +604,14 @@ void SpiceTokNoNewline(void)
     while (nexttok == NULL) {
 	contline = getc(infile);
 	if (contline == '*') {
-	   GetNextLine(WHITESPACE_DELIMITER);
-	   SkipNewLine(NULL);
+	   char testline = ' ';
+	   while ((testline == ' ') || (testline == '\t'))
+	      testline = getc(infile);
+           if (testline != '\n') {
+              ungetc(testline, infile);
+	      GetNextLine(WHITESPACE_DELIMITER);
+	      SkipNewLine(NULL);
+	   }
 	   continue;
 	}
 	else if (contline != '+') {

base/spice.c

@@ -43,6 +43,7 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #include "print.h"
 #include "query.h"
 #include "objlist.h"
+#include "netcmp.h"
 
 // Global storage for parameters from .PARAM
 struct hashdict spiceparams;
@@ -519,7 +520,7 @@ void ReadSpiceFile(char *fname, int filenum, struct cellstack **CellStackPtr,
   char *eqptr, devtype, in_subckt;
   struct keyvalue *kvlist = NULL;
   char inst[MAX_STR_LEN], model[MAX_STR_LEN], instname[MAX_STR_LEN];
-  struct nlist *tp;
+  struct nlist *tp, *tpsave;
   struct objlist *parent, *sobj, *nobj, *lobj, *pobj;
 
   inst[MAX_STR_LEN-1] = '\0';
@@ -557,6 +558,7 @@ void ReadSpiceFile(char *fname, int filenum, struct cellstack **CellStackPtr,
 
       snprintf(model, MAX_STR_LEN-1, "%s", nexttok);
       tp = LookupCellFile(nexttok, filenum);
+      tpsave = NULL;
 
       /* Check for name conflict with duplicate cell names	*/
       /* This may mean that the cell was used before it was	*/
@@ -595,11 +597,46 @@ void ReadSpiceFile(char *fname, int filenum, struct cellstack **CellStackPtr,
          tp = LookupCellFile(nexttok, filenum);
       }
       else if (tp != NULL) {	/* Make a new definition for an empty cell */
-	 FreePorts(nexttok);
-	 CellDelete(nexttok, filenum);	/* This removes any PLACEHOLDER flag */
-	 CellDef(model, filenum);
-	 tp = LookupCellFile(model, filenum);
-	 update = 1;	/* Will need to update existing instances */
+	 /* Handle issue with SPICE read after verilog, where a placeholder
+	  * was created from the verilog.  (1) If the pin names are "1", "2",
+	  * "3", then this is a SPICE placeholder, and just remove the CellDef
+	  * and re-create it.  Otherwise, create new cell "_PLACEHOLDER_".
+	  * (2) After encountering .ends, run MatchPins between the two cells.
+	  * (3) delete the original cell and rename the new cell.
+	  */
+	 int i = 1;
+	 char pname[10];
+	 for (pobj = tp->cell; pobj && pobj->type == PORT; pobj = pobj->next) {
+	     sprintf(pname, "%d", i);
+	     if (!matchnocase(pobj->name, pname)) break;
+	     i++;
+	 }
+	 if ((pobj == NULL) || (pobj->type != PORT)) {
+	    /* This is a SPICE placeholder created because the cell was instanced
+	     * before it was defined.  However, the pins can be assumed to be in
+	     * the correct order, and pin reordering does not need to be done.
+	     */
+	    FreePorts(nexttok);
+	    CellDelete(nexttok, filenum);	/* This removes any PLACEHOLDER flag */
+	    CellDef(model, filenum);
+	    tp = LookupCellFile(model, filenum);
+	    update = 1;	/* Will need to update existing instances */
+	 }
+	 else {
+	    /* This is (probably) a verilog placeholder created because the
+	     * verilog was read before the (SPICE) definitions.  The verilog
+	     * netlist should have named the pins of the parent cell.  However,
+	     * there is no guarantee the order of pins is correct.  The MatchPins()
+	     * routine from netcmp.c can be used here to match the cell against
+	     * the placeholder, and reorder the pins in all instances to match.
+	     * Note that we cannot just reorder the SPICE pins to match the
+	     * verilog order, because there may be other SPICE netlists which
+	     * instance the cell with the correct SPICE port order.
+	     */
+	     tpsave = tp;
+             CellDef("_PLACEHOLDER_", filenum);
+             tp = LookupCellFile("_PLACEHOLDER_", filenum);
+	 }
       }
       else if (tp == NULL) {	/* Completely new cell, no name conflict */
          CellDef(model, filenum);
@@ -691,6 +728,38 @@ skip_ends:
       if (*CellStackPtr) PopStack(CellStackPtr);
       if (*CellStackPtr) ReopenCellDef((*CellStackPtr)->cellname, filenum);
       SkipNewLine(NULL);
+
+      if (tpsave != NULL) {
+	 struct nlist *tpplace;
+	 char *savename;
+
+	 /* Handle a placeholder from a verilog file that has been replaced
+	  * by a netlist with pins in a different order.  The pins need to
+	  * be matched, corrected in the original cell and all instances,
+	  * and the new cell deleted.
+	  */
+
+	 Printf("Verilog placeholder %s replaced by SPICE definition\n",
+		tpsave->name);
+         tpplace = LookupCellFile("_PLACEHOLDER_", filenum);
+	 /* MatchPins is part of netcmp and normally Circuit2 is the
+	  * circuit being matched, so set Circuit2 to the original
+	  * verilog black-box cell, and MatchPins() will force its
+	  * pins to be rearranged to match the SPICE definition just
+	  * read.
+	  */
+	 Circuit2 = tpsave;
+	 MatchPins(tpplace, tpsave, 0);
+	 savename = strsave(tpsave->name);
+	 /* Now the original verilog black-box cell can be removed */
+	 FreePorts(savename);
+	 CellDelete(savename, filenum);
+	 /* And _PLACEHOLDER_ is renamed to the original name of the cell. */
+	 CellRehash("_PLACEHOLDER_", savename, filenum);
+	 tpsave = NULL;
+	 Circuit2 = NULL;
+	 FREE(savename);
+      }
     }
     else if (matchnocase(nexttok, ".MODEL")) {
       unsigned char class = CLASS_SUBCKT;

scripts/configure

@@ -6302,7 +6302,7 @@ fi
 
     *darwin*)
       SHDLIB_EXT=".dylib"
-      LDDL_FLAGS="-dynamiclib -flat_namespace -undefined suppress -noprebind"
+      LDDL_FLAGS="-dynamiclib -undefined dynamic_lookup"
       LDFLAGS="${LDFLAGS} ${LIB_SPECS}"
       CFLAGS="${CFLAGS} ${X_CFLAGS} ${INC_SPECS} -I/sw/include -fno-common"
       ;;

scripts/configure.in

@@ -1033,7 +1033,7 @@ fi
 
     *darwin*)
       SHDLIB_EXT=".dylib"
-      LDDL_FLAGS="-dynamiclib -flat_namespace -undefined suppress -noprebind"
+      LDDL_FLAGS="-dynamiclib -undefined dynamic_lookup"
       LDFLAGS="${LDFLAGS} ${LIB_SPECS}"
       CFLAGS="${CFLAGS} ${X_CFLAGS} ${INC_SPECS} -I/sw/include -fno-common"
       ;;