Merge branch 'master' into netgen-1.5

(1) Fixed the series sorting, which needed to be modified to match
the parallel sorting routine. This fixes occasional property errors with series-connected devices such as resistors. (2) Added a method to associate properties with specific pins when pins are permutable. This allows netgen to properly check a value like source/drain area when the definition of source and drain has changed due to permutation of the device. (3) Added a "property" command extension "associate" to associate a property with a pin, for use with the method described in (2).
2026-08-26 07:56:56 +02:00 · 2022-12-16 02:00:03 -05:00 · 2022-12-15 21:34:56 -05:00 · 2022-11-17 02:00:01 -05:00 · 2022-11-16 12:37:05 -05:00 · 2022-11-05 02:00:01 -04:00
25 changed files with 1126 additions and 508 deletions
@@ -1 +1 @@
-1.5.221
+1.5.243
@@ -131,7 +131,7 @@ if format = 1, use the actel .pin file format
  struct nlist *tp;
  struct objlist *ob, *ob2;
  char *ptr;
-  char physicalpin[200];
+  char physicalpin[MAX_STR_LEN];

  tp = LookupCell(name);
  if (tp == NULL) return;
@@ -176,4 +176,6 @@ extern int open(char *path, int oflag, ...); /* HPUX has it in <sys/fcntl.h> */
 #define FALSE 0
 #endif

+#define MAX_STR_LEN 256
+
 #endif /* _CONFIG_H */
@@ -629,7 +629,7 @@ struct embed *FlattenEmbeddingTree(struct embed *E)
 int LenEmbed(char *prefix, struct nlist *np, struct embed *E, int flatten)
 /* return the number of characters required to print element E */
 {
-  char longstr[200];
+  char longstr[MAX_STR_LEN];

  if (E == NULL) return(0);
  if (E->left == NULL && E->right == NULL) {
@@ -668,7 +668,7 @@ void PrintEmb(FILE *outfile, char *prefix, struct nlist *np,
    struct objlist *ob;
    char *instancename;
    struct nlist *np2;
-    char name[200];
+    char name[MAX_STR_LEN];

    ob = InstanceNumber(np,E->instancenumber);
    instancename = ob->instance.name;
@@ -706,7 +706,7 @@ void PrintEmbed(FILE *outfile, char *prefix, struct nlist *np,
    struct objlist *ob;
    char *instancename;
    struct nlist *np2;
-    char name[200];
+    char name[MAX_STR_LEN];

    ob = InstanceNumber(np,E->instancenumber);
    instancename = ob->instance.name;
@@ -167,7 +167,7 @@ char *ReadExt(char *fname, int doflat, int *fnum)
  int filenum;

  if ((filenum = OpenParseFile(fname, *fnum)) < 0) {
-    char name[100];
+    char name[MAX_STR_LEN];

    SetExtension(name, fname, EXT_EXTENSION);
    if ((filenum = OpenParseFile(name, *fnum)) < 0) {
@@ -208,7 +208,7 @@ char *ReadExt(char *fname, int doflat, int *fnum)
    else if (match(nexttok, "style"))  SkipNewLine(NULL);
    else if (match(nexttok, "resistclasses"))  SkipNewLine(NULL);
    else if (match(nexttok, "node")) {
-      char name[200];
+      char name[MAX_STR_LEN];

      /* No cell is generated until at least one valid "node" or "use"	*/
      /* has been read in the file.					*/
@@ -223,8 +223,8 @@ char *ReadExt(char *fname, int doflat, int *fnum)
      SkipNewLine(NULL);
    }
    else if (match(nexttok, "equiv")) {
-      char name[200];
-      char name2[200];
+      char name[MAX_STR_LEN];
+      char name2[MAX_STR_LEN];
      SkipTok(NULL);
      GetExtName(name, nexttok);
      if (LookupObject(name,CurrentCell) == NULL) Node(name);
@@ -235,8 +235,8 @@ char *ReadExt(char *fname, int doflat, int *fnum)
      SkipNewLine(NULL);
    }
    else if (match(nexttok, "device")) {
-      char dev_name[100], dev_class[100];
-      char gate[200], drain[200], source[200], subs[200];
+      char dev_name[MAX_STR_LEN], dev_class[MAX_STR_LEN];
+      char gate[MAX_STR_LEN], drain[MAX_STR_LEN], source[MAX_STR_LEN], subs[MAX_STR_LEN];
      char inststr[64];
      SkipTok(NULL);
      strcpy(dev_class, nexttok);
@@ -306,8 +306,8 @@ char *ReadExt(char *fname, int doflat, int *fnum)
      SkipNewLine(NULL);
    }
    else if (match(nexttok, "fet")) {	/* old-style FET record */
-      char fet_class[100];
-      char gate[200], drain[200], source[200], subs[200];
+      char fet_class[MAX_STR_LEN];
+      char gate[MAX_STR_LEN], drain[MAX_STR_LEN], source[MAX_STR_LEN], subs[MAX_STR_LEN];
      char inststr[64];
      SkipTok(NULL);
      strcpy(fet_class, nexttok);
@@ -365,7 +365,7 @@ char *ReadExt(char *fname, int doflat, int *fnum)
 	SkipNewLine(NULL);
      }
      else {
-        char ctop[200], cbot[200], cdummy[200];
+        char ctop[MAX_STR_LEN], cbot[MAX_STR_LEN], cdummy[MAX_STR_LEN];
 	SkipTok(NULL);
        GetExtName(ctop, nexttok);
 	SkipTok(NULL);
@@ -375,8 +375,8 @@ char *ReadExt(char *fname, int doflat, int *fnum)
      }
    }
    else if (match(nexttok, "use")) {
-      char name[200];
-      char instancename[200];
+      char name[MAX_STR_LEN];
+      char instancename[MAX_STR_LEN];
      char *basename;

      /* No cell is generated until at least one valid "node" or "use"	*/
@@ -390,7 +390,7 @@ char *ReadExt(char *fname, int doflat, int *fnum)
      SkipTok(NULL);
      GetExtName(name, nexttok);
      if ((basename = strrchr(name,'/')) != NULL) {
-	char tmp[200];
+	char tmp[MAX_STR_LEN];
 	strcpy(tmp, basename+1);
 	strcpy(name, tmp);
      }
@@ -405,8 +405,8 @@ char *ReadExt(char *fname, int doflat, int *fnum)
      SkipNewLine(NULL);
    }
    else if (match(nexttok, "merge")) {
-      char name[200];
-      char name2[200];
+      char name[MAX_STR_LEN];
+      char name2[MAX_STR_LEN];
      SkipTok(NULL);
      GetExtName(name, nexttok);
      SkipTok(NULL);
@@ -640,7 +640,7 @@ char *ReadSim(char *fname, int *fnum)
  double simscale = 1.0;

  if ((filenum = OpenParseFile(fname, *fnum)) < 0) {
-    char name[100];
+    char name[MAX_STR_LEN];

    SetExtension(name, fname, SIM_EXTENSION);
    if (OpenParseFile(name, *fnum) < 0) {
@@ -670,7 +670,7 @@ char *ReadSim(char *fname, int *fnum)
      SkipNewLine(NULL);
    }
    else if (match(nexttok, "n")) {
-      char gate[200], drain[200], source[200];
+      char gate[MAX_STR_LEN], drain[MAX_STR_LEN], source[MAX_STR_LEN];
      char inststr[25], *instptr = NULL;

      SkipTok(NULL);
@@ -714,7 +714,7 @@ char *ReadSim(char *fname, int *fnum)
      LinkProperties("n", kvlist);
    }
    else if (match(nexttok, "p")) {
-      char gate[200], drain[200], source[200];
+      char gate[MAX_STR_LEN], drain[MAX_STR_LEN], source[MAX_STR_LEN];
      char inststr[25], *instptr = NULL;
      SkipTok(NULL);
      GetExtName(gate, nexttok);
@@ -754,7 +754,7 @@ char *ReadSim(char *fname, int *fnum)
      LinkProperties("p", kvlist);
    }
    else if (match(nexttok, "e")) {	/* 3-port capacitors (poly/poly2) */
-      char gate[200], drain[200], source[200];
+      char gate[MAX_STR_LEN], drain[MAX_STR_LEN], source[MAX_STR_LEN];
      char inststr[25], *instptr = NULL;
      SkipTok(NULL);
      GetExtName(gate, nexttok);
@@ -788,7 +788,7 @@ char *ReadSim(char *fname, int *fnum)
      E(fname, instptr, gate, drain, source);
    }
    else if (match(nexttok, "b")) {		/* bipolars added by Tim 7/16/96 */
-      char base[200], emitter[200], collector[200];
+      char base[MAX_STR_LEN], emitter[MAX_STR_LEN], collector[MAX_STR_LEN];
      char inststr[25], *instptr = NULL;
      SkipTok(NULL);
      GetExtName(base, nexttok);
@@ -826,7 +826,7 @@ char *ReadSim(char *fname, int *fnum)
 	SkipNewLine(NULL);
      }
      else {
-        char ctop[200], cbot[200], cdummy[200];
+        char ctop[MAX_STR_LEN], cbot[MAX_STR_LEN], cdummy[MAX_STR_LEN];
        SkipTok(NULL);
        GetExtName(ctop, nexttok);
        if (LookupObject(ctop, CurrentCell) == NULL)
@@ -851,7 +851,7 @@ char *ReadSim(char *fname, int *fnum)
 	SkipNewLine(NULL);
      }
      else {
-        char rtop[200], rbot[200];
+        char rtop[MAX_STR_LEN], rbot[MAX_STR_LEN];
        SkipTok(NULL);
        GetExtName(rtop, nexttok);
        if (LookupObject(rtop, CurrentCell) == NULL)
@@ -875,7 +875,7 @@ char *ReadSim(char *fname, int *fnum)
 	SkipNewLine(NULL);
      }
      else {
-        char rtop[200], rbot[200], rdummy[200];
+        char rtop[MAX_STR_LEN], rbot[MAX_STR_LEN], rdummy[MAX_STR_LEN];
 	char inststr[25], *instptr = NULL;
        SkipTok(NULL);
        GetExtName(rdummy, nexttok);
@@ -917,7 +917,7 @@ char *ReadSim(char *fname, int *fnum)
      SkipNewLine(NULL);
    }
    else if (match(nexttok, "=")) {
-      char node1[200], node2[200];
+      char node1[MAX_STR_LEN], node2[MAX_STR_LEN];
      SkipTok(NULL);
      GetExtName(node1, nexttok);
      SkipTok(NULL);
@@ -53,7 +53,7 @@ void flattenCell(char *name, int file)
  struct nlist *ChildCell;
  struct objlist *tmp, *ob2, *ob3;
  int	notdone, rnodenum;
-  char	tmpstr[200];
+  char	tmpstr[MAX_STR_LEN];
  int	nextnode, oldmax;
 #if !OLDPREFIX
  int     prefixlength;
@@ -66,9 +66,13 @@ void flattenCell(char *name, int file)
  else
     ThisCell = LookupCellFile(name, file);
  if (ThisCell == NULL) {
-    Printf("No cell %s found.\n", name);
+    Printf("No cell %s (%d) found.\n", name, file);
    return;
  }
+
+  /* Placeholder cells must not be flattened */
+  if (ThisCell->flags & CELL_PLACEHOLDER) return;
+
  FreeNodeNames(ThisCell);

  ParentParams = ThisCell->cell;
@@ -239,6 +243,13 @@ void flattenCell(char *name, int file)
  ThisCell->dumped = 1;		/* indicate cell has been flattened */
 }

+/* Structure used to keep track of nodes needing checking */
+
+struct linkednode {
+    int node;
+    struct linkednode *next;
+};
+
 /*--------------------------------------------------------------*/
 /* flattenInstancesOf --					*/
 /*								*/
@@ -261,6 +272,7 @@ int flattenInstancesOf(char *name, int fnum, char *instance)
  struct nlist *ThisCell;
  struct  nlist *ChildCell;
  struct objlist *tmp, *ob2, *ob3;
+  struct linkednode *checknodes = NULL, *newlnode, *chknode;
  int	notdone, rnodenum;
  char	tmpstr[1024];
  int	nextnode, oldmax, numflat = 0;
@@ -278,16 +290,20 @@ int flattenInstancesOf(char *name, int fnum, char *instance)
  }
  else {
    if (Debug) 
-       Printf("Flattening instances of %s within cell: %s\n", instance, name);
+       Printf("Flattening instances of %s within cell: %s (%d)\n", instance,
+			name, fnum);
    if (fnum == -1)
       ThisCell = LookupCell(name);
    else
       ThisCell = LookupCellFile(name, fnum);
    if (ThisCell == NULL) {
-      Printf("No cell %s found.\n", name);
+      Printf("No cell %s (%d) found.\n", name, fnum);
      return 0;
    }
  }
+  /* Placeholder cells must not be flattened */
+  if (ThisCell->flags & CELL_PLACEHOLDER) return 0;
+
  FreeNodeNames(ThisCell);

  ParentParams = ThisCell->cell;
@@ -408,6 +424,16 @@ int flattenInstancesOf(char *name, int fnum, char *instance)
 	          }
 	          UpdateNodeNumbers(ChildStart, tmp->node, ob2->node);
 	     }
+	     else if (tmp->node == -1) {
+		 /* Opposite case:  If child port is an unconnected node, then	*/
+		 /* removing the instance may make the parent node become	*/
+		 /* unconnected.  For now, just record the node number.  At the	*/
+		 /* end we'll check if these nodes are actually disconnected.	*/
+		 newlnode = (struct linkednode *)MALLOC(sizeof(struct linkednode));
+		 newlnode->node = ob2->node;
+		 newlnode->next = checknodes;
+		 checknodes = newlnode;
+	     }

 	     /* in pathological cases, the lengths of the port lists may
              * change.  This is an error, but that is no reason to allow
@@ -590,6 +616,29 @@ int flattenInstancesOf(char *name, int fnum, char *instance)
      NextObj = ParentParams;
    }				/* repeat until no more instances found */
  }
+
+  /* Check nodes that may have become disconnected after child flattening */
+  while (checknodes != NULL) {
+     struct objlist *portnode = NULL;
+
+     chknode = checknodes;
+     checknodes = checknodes->next;
+
+     for (ob3 = ThisCell->cell; ob3; ob3 = ob3->next) {
+	if ((ob3->type != PORT) && (portnode == NULL))
+	   break;
+	else if ((ob3->type == PORT) && (ob3->node == chknode->node))
+	   portnode = ob3;
+	else if ((ob3->type >= FIRSTPIN) && (ob3->node == chknode->node))
+	   break;
+     }
+     if ((ob3 == NULL) && (portnode != NULL)) {
+        /* Port became disconnected when child was flattened */
+        portnode->node = -1;
+     }
+     FREE(chknode);
+  }
+
  CacheNodeNames(ThisCell);
  ThisCell->dumped = 1;		/* indicate cell has been flattened */
  return numflat;
@@ -681,7 +730,7 @@ void convertGlobalsOf(char *name, int fnum, char *instance)
      else
         ThisCell = LookupCellFile(name, fnum);
      if (ThisCell == NULL) {
-	 Printf("No cell %s found.\n", name);
+	 Printf("No cell %s (%d) found.\n", name, fnum);
 	 return;
      }
   }
@@ -1111,7 +1160,7 @@ int UniquePins(char *name, int filenum)
      ThisCell = LookupCellFile(name, filenum);

   if (ThisCell == NULL) {
-      Printf("No cell %s found.\n", name);
+      Printf("No cell %s (%d) found.\n", name, filenum);
      return 0;
   }

@@ -1128,12 +1177,33 @@ int UniquePins(char *name, int filenum)
   firstport = (struct objlist **)CALLOC(maxnode + 1, sizeof(struct objlist *));

   portcount = FIRSTPIN;
+   lob = NULL;
   for (ob = ThisCell->cell; ob != NULL; ob = ob->next) {
      if (ob->type != PORT) break;
      if (ob->node > 0) {
 	 nodecount[ob->node]++;
 	 if (nodecount[ob->node] == 2) {
-	    Printf("Duplicate pin %s in cell %s\n", ob->name, ThisCell->name);
+	    if (!(*matchfunc)(firstport[ob->node]->name, ob->name)) {
+	       Printf("Pins %s and %s are shorted in cell %s (%d)\n", ob->name,
+			firstport[ob->node]->name, ThisCell->name, ThisCell->file);
+	       /* Do not count this as a duplicate pin. */
+	       nodecount[ob->node]--;
+	       /* Move the pin adjacent to the one it is shorted to (if it	
+		* isn't already);  this will make the work of MatchPins() easier.
+		*/
+	       if (firstport[ob->node]->next != ob) {
+	          lob->next = ob->next;
+	          ob->next = firstport[ob->node]->next;
+		  firstport[ob->node]->next = ob;
+	          ob = lob;
+	       }
+	       lob = ob;
+	       continue;
+	    }
+	    else {
+	       Printf("Duplicate pin %s in cell %s (%d)\n", ob->name,
+				ThisCell->name, filenum);
+	    }
 	 }
 	 if (nodecount[ob->node] > 1) {
 	    /* Remove this node;  prep for removal by marking with UNKNOWN */
@@ -1148,6 +1218,7 @@ int UniquePins(char *name, int filenum)
 	 }
      }
      portcount++;
+      lob = ob;
   }

   if (needscleanup)
@@ -1332,7 +1403,7 @@ int CleanupPins(char *name, int filenum)
      ThisCell = LookupCellFile(name, filenum);

   if (ThisCell == NULL) {
-      Printf("No cell %s found.\n", name);
+      Printf("No cell %s (%d) found.\n", name, filenum);
      return 0;
   }

@@ -1599,19 +1670,22 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
 		}
 	    }
 	    if (match) {
-		if (ecomp->cell1 && (ecomp->num1 > 0)) {
+		if (ecomp->cell1 && (ecomp->num1 > 0) &&
+				(!(ecomp->cell1->flags & CELL_PLACEHOLDER))) {
 		    Fprintf(stdout, "Flattening instances of %s in cell %s (%d)"
 				" makes a better match\n", ecomp->cell1->name,
 				name1, file1);
 		    flattenInstancesOf(name1, file1, ecomp->cell1->name); 
+		    modified++;
 		}
-		if (ecomp->cell2 && (ecomp->num2 > 0)) {
+		if (ecomp->cell2 && (ecomp->num2 > 0) &&
+				(!(ecomp->cell2->flags & CELL_PLACEHOLDER))) {
 		    Fprintf(stdout, "Flattening instances of %s in cell %s (%d)"
 				" makes a better match\n", ecomp->cell2->name,
 				name2, file2);
 		    flattenInstancesOf(name2, file2, ecomp->cell2->name); 
+		    modified++;
 		}
-		modified++;
 	    }

 	    /* Reset or apply the count adjustments */
@@ -1688,13 +1762,21 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
 		}
 	    }
 	    if (match) {
-		if (ecomp->cell2) {
-		    Fprintf(stdout, "Flattening instances of %s in cell %s (%d)"
+
+		/* Don't flatten if cell1 is a black box, because it	*/
+		/* can't also be flattened.				*/
+
+		if ((ecomp->num1 == 0) || (ecomp->cell1->class !=
+				CLASS_MODULE)) {
+
+		    if (ecomp->cell2 && !(ecomp->cell2->flags & CELL_PLACEHOLDER)) {
+		    	Fprintf(stdout, "Flattening instances of %s in cell %s (%d)"
 				" makes a better match\n", ecomp->cell2->name,
 				name2, file2);
-		    flattenInstancesOf(name2, file2, ecomp->cell2->name); 
+		    	flattenInstancesOf(name2, file2, ecomp->cell2->name); 
+		    	modified++;
+		    }
 		}
-		modified++;
 	    }

 	    /* Reset or apply the count adjustments */
@@ -1718,7 +1800,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
 	}
 	
 	/* Case 3:  Cell1 class is a subcircuit, and flattening	*/
-	/* it (without regard to cell1) improves the matching.	*/
+	/* it (without regard to cell2) improves the matching.	*/

 	else if ((ecomp->num1 != ecomp->num2) && (ecomp->cell1 != NULL) &&
 			(ecomp->num1 != 0) && (ecomp->cell1->class == CLASS_SUBCKT)) {
@@ -1746,13 +1828,21 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
 		}
 	    }
 	    if (match) {
-		if (ecomp->cell1) {
-		    Fprintf(stdout, "Flattening instances of %s in cell %s (%d)"
+
+		/* Don't flatten if cell2 is a black box, because it	*/
+		/* can't also be flattened.				*/
+
+		if ((ecomp->num2 == 0) || (ecomp->cell2->class !=
+				CLASS_MODULE)) {
+
+		    if (ecomp->cell1 && !(ecomp->cell1->flags & CELL_PLACEHOLDER)) {
+		    	Fprintf(stdout, "Flattening instances of %s in cell %s (%d)"
 				" makes a better match\n", ecomp->cell1->name,
 				name1, file1);
-		    flattenInstancesOf(name1, file1, ecomp->cell1->name); 
+		    	flattenInstancesOf(name1, file1, ecomp->cell1->name); 
+		        modified++;
+		    }
 		}
-		modified++;
 	    }

 	    /* Reset or apply the count adjustments */
@@ -33,7 +33,7 @@ void STRCPY(char *dest, char *source)

 int main(int argc, char *argv[])
 {
-  char cell1[200], cell2[200];
+  char cell1[MAX_STR_LEN], cell2[MAX_STR_LEN];

  Debug = 0;
  if (argc != 1) {
@@ -875,7 +875,11 @@ struct FormattedList *FormatBadNodeFragment(struct Node *N)
      for (n = pins[i]->subelement->element->nodelist; n != NULL; n = n->next){
 	if (n->pin_magic == pins[i]->subelement->pin_magic) {
 	  if ((permute == 0) && (ob->instance.name != NULL)) {
-	     pinname = ob->name + strlen(ob->instance.name) + 1;
+	     /* Handle "port_match_error" */
+	     if ((ob->name[0] == 'p') && !strcmp(ob->name, "port_match_error"))
+		pinname = ob->name;
+	     else
+	        pinname = ob->name + strlen(ob->instance.name) + 1;
 	  }
 	  else if (ob->instance.name != NULL) {
 	     char *pinsave = pinname;
@@ -4210,7 +4214,11 @@ void series_sort(struct objlist *ob1, struct nlist *tp1, int idx1, int run)
   struct property *kl;
   struct valuelist *vl, *sl;
   int i, p, sval, merge_type;
-   double cval, slop;
+   // double cval, slop;
+   int has_crit;
+   char ca, co;
+   double tval, tslop;
+   double aval, pval, oval, aslop, pslop;

   obn = ob1->next;
   for (i = 0; i < idx1; i++) obn = obn->next;
@@ -4223,55 +4231,94 @@ void series_sort(struct objlist *ob1, struct nlist *tp1, int idx1, int run)

   obp = obn;
   sval = 1;
-   cval = slop = 0.0;
+   pval = aval = oval = 0.0;
   for (i = 0; i < run; i++) {
-      sl = NULL;
+      has_crit = FALSE;
      merge_type = MERGE_NONE;
+      ca = co = (char)0;
+
      for (p = 0;; p++) {
 	 vl = &(obp->instance.props[p]);
 	 if (vl->type == PROP_ENDLIST) break;
 	 if (vl->key == NULL) continue;
         if ((*matchfunc)(vl->key, "S")) {
 	    sval = vl->value.ival;
-	    sl = vl;
+	    continue;
+	 }
+         kl = (struct property *)HashLookup(vl->key, &(tp1->propdict));
+	 if (kl == NULL) continue;		/* Ignored property */
+
+	 /* Get the property value and slop.  Promote if needed.  Save	*/
+	 /* property and slop as type double so they can be sorted.	*/
+
+	 if ((vl->type == PROP_STRING || vl->type == PROP_EXPRESSION) &&
+		  	(kl->type != vl->type))
+	    PromoteProperty(kl, vl, obp, tp1);
+	 if (vl->type == PROP_INTEGER) {
+	    tval = (double)vl->value.ival;
+	    tslop = (double)kl->slop.ival;
+	 }
+	 else if (vl->type == PROP_STRING) {
+	    /* This is unlikely---no method to merge string properties! */
+	    tval = (double)vl->value.string[0]
+			+ (double)vl->value.string[1] / 10.0;
+	    tslop = (double)0;
 	 }
 	 else {
-	    kl = (struct property *)HashLookup(vl->key, &(tp1->propdict));
-	    if (kl && (kl->merge & (MERGE_S_ADD | MERGE_S_PAR))) {
-		if (vl->type == PROP_INTEGER) {
-		   cval = (double)vl->value.ival;
-		   slop = (double)kl->slop.ival;
-		}
-		else {
-		   cval = vl->value.dval;
-		   slop = kl->slop.dval;
-		}
-	 	merge_type = kl->merge & (MERGE_S_ADD | MERGE_S_PAR);
+	    tval = vl->value.dval;
+	    tslop = kl->slop.dval;
+	 }
+
+	 if (kl->merge & MERGE_S_CRIT) {
+	    has_crit = TRUE;
+	    pval = tval;
+	    pslop = tslop;
+	 }
+	 else if (kl->merge & (MERGE_S_ADD | MERGE_S_PAR)) {
+	    if ((ca == (char)0) || (toupper(vl->key[0]) > ca)) {
+	       merge_type = kl->merge & (MERGE_S_ADD | MERGE_S_PAR);
+	       aval = tval;
+	       aslop = tslop;
+	       ca = toupper(vl->key[0]);
 	    }
 	 }
+	 else if ((co == (char)0) || (toupper(vl->key[0]) > co)) {
+	    oval = tval;
+	    co = toupper(vl->key[0]);
+	 }
      }
-      if (merge_type == MERGE_S_ADD) {
-	 proplist[i].value = cval * (double)sval;
-         proplist[i].slop = slop;
-         proplist[i].avalue = 0;
-	 if (sl) sl->value.ival = 1;
-      }
-      else if (merge_type == MERGE_S_PAR) {
-	 proplist[i].value = cval / (double)sval;
-         proplist[i].slop = slop;
-         proplist[i].avalue = 0;
-	 if (sl) sl->value.ival = 1;
+      if (has_crit == TRUE) {
+	 /* If there is a critical value, then sort first   */
+	 /* by critical value				    */
+	 proplist[i].value = pval;
+	 proplist[i].slop = pslop;
+
+	 /* then sort on additive value times S	*/
+	 /* or on non-additive value.		*/
+         if (merge_type == MERGE_S_ADD)
+	    proplist[i].avalue = aval * (double)sval;
+         else if (merge_type == MERGE_S_PAR)
+	    proplist[i].avalue = aval / (double)sval;
+	 else
+	    proplist[i].avalue = (double)sval;
      }
      else {
-	 /* Components which declare no series addition method stay unsorted */
-	 proplist[i].value = (double)0;
-	 proplist[i].avalue = (double)0;
-         proplist[i].slop = (double)1E-6;
+         if (merge_type != MERGE_NONE) {
+	    proplist[i].value = aval;
+	    proplist[i].slop = aslop;
+	    proplist[i].avalue = (double)sval;
+	 }
+	 else {
+	    proplist[i].value = (double)sval;
+	    proplist[i].slop = (double)0;
+	    proplist[i].avalue = oval;
+	 }
      }
      proplist[i].idx = i;
      proplist[i].ob = obp;
      obp = obp->next;
   }
+
   obn = obp;	/* Link from last property */

   qsort(&proplist[0], run, sizeof(propsort), compsort);
@@ -4594,8 +4641,8 @@ void PropertySortAndCombine(struct objlist *pre1, struct nlist *tp1,
      /* and manage the topology.  Note that at this point devices have	   */
      /* already been combined if all critical properties match, so any	   */
      /* parallel devices remaining are not considered mergeable unless as */
-      /* a last resort.  Parallel devices need to be checked for swapping, */
-      /* however.  So the steps are:					   */
+      /* a last resort.  Devices also need to be checked for swapping.	   */
+      /* So the steps are:					   	   */
      /* 1) Find parallel devices with more elements in one circuit than   */
      /*    in the other.  If non-summing parameters of interest match,	   */
      /*    then merge all devices that can be merged until both sides	   */
@@ -4608,6 +4655,10 @@ void PropertySortAndCombine(struct objlist *pre1, struct nlist *tp1,
      /*    circuits.  Check if critical parameters match between the 	   */
      /*    circuits.  If not, check if swapping devices in circuit1	   */
      /*    makes a better match to circuit2.			  	   */
+      /* 4) Find series devices that have the same number in both 	   */
+      /*    circuits.  Check if critical parameters match between the 	   */
+      /*    circuits.  If not, check if swapping devices in circuit1	   */
+      /*    makes a better match to circuit2.			  	   */

      /* Case 1:  Parallel devices with more elements in one circuit	*/

@@ -5001,6 +5052,11 @@ int PropertyOptimize(struct objlist *ob, struct nlist *tp, int run, int series,
 		  // find ith record in ob
 		  p = 0;
 		  for (ob2 = ob; p != i; ob2 = ob2->next, p++);
+		  /* Sanity check */
+		  if (ob2->type != PROPERTY) {
+    		     Fprintf(stderr, "Incorrect property run count!\n");
+		     continue;
+		  }
 		  // Count entries, add one, reallocate
 		  for (p = 0;; p++) {
 		     vl = &ob2->instance.props[p];
@@ -5308,13 +5364,14 @@ void
 #endif
 PropertyCheckMismatch(struct objlist *tp1, struct nlist *tc1,
 	char *inst1, struct objlist *tp2, struct nlist *tc2,
-	char *inst2, int do_print, int do_list, int *count,
-	int *rval)
+	char *inst2, struct Element *E1, struct Element *E2,
+	int do_print, int do_list, int *count, int *rval)
 {
   int mismatches = 0;
   int len2, *check2;
   struct property *kl1, *kl2, *klt;
   struct valuelist *vl1, *vl2;
+   char *vl1key;
   int i, j;
   int islop;
   int ival1, ival2;
@@ -5418,22 +5475,71 @@ PropertyCheckMismatch(struct objlist *tp1, struct nlist *tc1,
 	 }
      }

+      /* If the property is associated with a pin, then		*/
+      /* determine if the pin is permutable;  If so, then	*/
+      /* determine if the pins are swapped between the two	*/
+      /* elements.  If so, then swap the property keys.		*/
+
+      vl1key = vl1->key;
+      if (kl1->pin != NULL) {
+	 struct objlist *tob1, *tob2;
+	 struct NodeList *nl1, *nl2;
+	 struct property *kla;
+	 struct valuelist *vla;
+         int k;
+
+	 nl1 = E1->nodelist;
+	 for (tob1 = tc1->cell; tob1 && tob1->type == PORT; tob1 = tob1->next) {
+	     if ((*matchfunc)(tob1->name, kl1->pin)) break;
+	     nl1 = nl1->next;
+	 }
+	 if (tob1->type == PORT) {
+	     /* Found the node list record corresponding to the given pin. */
+	     /* Now find the pin corresponding to the matching node. */
+	     nl2 = E2->nodelist;
+	     for (tob2 = tc1->cell; tob2 && tob2->type == PORT; tob2 = tob2->next) {
+		if (nl2->node->nodeclass == nl1->node->nodeclass) break;
+	     	nl2 = nl2->next;
+	     }
+	     if (nl2->node->nodeclass == nl1->node->nodeclass) {
+		 if (tob2 != tob1) {	/* Element pins were swapped */
+		    /* Find the other property to swap with */
+		    for (k = 0;; k++) {
+         		vla = &(tp1->instance.props[k]);
+	 		if (vla->type == PROP_ENDLIST) break;
+			if (vla != vl1) {
+	       		    kla = (struct property *)HashLookup(vla->key,
+					&(tc1->propdict));
+			    if (kla && kla->pin)
+	     		        if ((*matchfunc)(tob2->name, kla->pin))
+				    break;
+			}
+		    }
+		    if (vla->type != PROP_ENDLIST) {
+			/* Swap vla->key and vl1->key */
+			vl1key = vla->key;
+		    }
+		 }
+	     }
+	 }
+      }
+
      /* Find the matching property in vl2. */

      for (j = 0;; j++) {
         vl2 = &(tp2->instance.props[j]);
 	 if (vl2->type == PROP_ENDLIST) break;
 	 if (check2[j] == 0)
-	    if ((*matchfunc)(vl1->key, vl2->key)) break;
+	    if ((*matchfunc)(vl1key, vl2->key)) break;
      }
      if (vl2->type == PROP_ENDLIST) {
 	 /* Check against M and S records;  a missing M or S	*/
 	 /* record is equivalent to M = 1 or S = 1.		*/

 	 if (vl1 != &mvl)
-	    if ((*matchfunc)(vl1->key, mvl.key)) vl2 = &mvl;
+	    if ((*matchfunc)(vl1key, mvl.key)) vl2 = &mvl;
 	 if (vl1 != &svl)
-	    if ((*matchfunc)(vl1->key, svl.key)) vl2 = &svl;
+	    if ((*matchfunc)(vl1key, svl.key)) vl2 = &svl;
      }
      if (vl2->type == PROP_ENDLIST) {
 	 /* vl1 had a property of interest that was not found	*/
@@ -5442,7 +5548,7 @@ PropertyCheckMismatch(struct objlist *tp1, struct nlist *tc1,
         if (do_print) {
 	    Fprintf(stdout, "%s vs. %s:\n", inst1, inst2);
 	    Fprintf(stdout, "Property %s in circuit1 has no matching "
-			"property in circuit2\n",  vl1->key);
+			"property in circuit2\n",  vl1key);
 	 }
 #ifdef TCL_NETGEN
         if (do_list) {
@@ -5779,14 +5885,15 @@ Tcl_Obj *
 #else
 void
 #endif
-PropertyMatch(struct objlist *ob1, int file1,
-		struct objlist *ob2, int file2,
+PropertyMatch(struct Element *E1, struct Element *E2,
 		int do_print, int do_list, int *retval)
 {
   struct nlist *tc1, *tc2;
-   struct objlist *tp1, *tp2, *obn1, *obn2, *tpc;
+   struct objlist *ob1, *ob2, *tp1, *tp2, *obn1, *obn2, *tpc;
   struct property *kl1, *kl2;
   struct valuelist *vl1, *vl2;
+   struct NodeList *nl1, *nl2;
+   int file1, file2;
   int t1type, t2type, run1, run2;
   int i, mismatches = 0, checked_one;
   int rval = 1;
@@ -5795,6 +5902,12 @@ PropertyMatch(struct objlist *ob1, int file1,
   Tcl_Obj *proplist = NULL, *mpair, *mlist;
 #endif

+   ob1 = E1->object;
+   ob2 = E2->object;
+
+   file1 = E1->graph;
+   file2 = E2->graph;
+
   tc1 = LookupCellFile(ob1->model.class, file1);
   tc2 = LookupCellFile(ob2->model.class, file2);

@@ -5882,12 +5995,14 @@ PropertyMatch(struct objlist *ob1, int file1,

   /* Check for no-connect pins in merged devices on both sides.	*/
   /* Both sides should either have no-connects marked, or neither.	*/
-   /* (Permutable pins may need to be handled correctly. . .		*/
+   /* Permutable pins need to be handled correctly.			*/

-   for (tp1 = ob1, tp2 = ob2; (tp1 != NULL) && tp1->type >= FIRSTPIN &&
-	    (tp2 != NULL) && tp2->type >= FIRSTPIN; tp1 = tp1->next, tp2 = tp2->next) {
+   for (tp1 = ob1, tp2 = ob2, nl1 = E1->nodelist; tp1 && tp2; tp1 = tp1->next, tp2 = tp2->next) {
      struct objlist *node1, *node2;

+      if ((tp1 != ob1) && (tp1->type <= FIRSTPIN)) break;
+      if ((tp2 != ob2) && (tp2->type <= FIRSTPIN)) break;
+
      if (file1 == Circuit1->file)
 	 node1 = Circuit1->nodename_cache[tp1->node];
      else
@@ -5898,22 +6013,45 @@ PropertyMatch(struct objlist *ob1, int file1,
      else
         node2 = Circuit2->nodename_cache[tp2->node];

+      if (node1->flags != node2->flags) {
+	 struct objlist *tp2b; 
+
+	 /* Find if there is permutable pin node with matching flags */
+	 /* Note that this is not rigorous, and should be better handled. */
+
+	 for (tp2b = ob2, nl2 = E2->nodelist; tp2b; tp2b = tp2b->next, nl2 = nl2->next) {
+       	     if ((tp2b != ob2) && (tp2b->type <= FIRSTPIN)) break;
+	     if (tp2b == tp2) continue;
+	     if (nl2->pin_magic == nl1->pin_magic) {
+      		 if (file2 == Circuit1->file)
+		    node2 = Circuit1->nodename_cache[tp2b->node];
+		 else
+		    node2 = Circuit2->nodename_cache[tp2b->node];
+	     }
+	     if (node1->flags == node2->flags) break;
+	 }
+      }
+
      /* NOTE: A "no-connect" node (multiple no-connects represented by a
       * single node) has non-zero flags.  A non-node entry in the cache
       * implies a node with zero flags.
       */
-      if (node1->flags != node1->flags) {
-	 Fprintf(stdout, "  Parallelized instances disagree on pin connections.\n");
-	 Fprintf(stdout, "    Circuit1 instance %s pin %s connections are %s (%d)\n",
+      if (node1->flags != node2->flags) {
+	 if (do_print) {
+	    Fprintf(stdout, "  Parallelized instances disagree on pin connections.\n");
+	    Fprintf(stdout, "    Circuit1 instance %s pin %s connections are %s (%d)\n",
 		    tp1->instance.name, node1->name,
 		    (node1->flags == 0) ? "tied together" : "no connects",
 		    node1->flags);
-	 Fprintf(stdout, "    Circuit2 instance %s pin %s connections are %s (%d)\n",
+	    Fprintf(stdout, "    Circuit2 instance %s pin %s connections are %s (%d)\n",
 		    tp2->instance.name, node2->name,
 		    (node2->flags == 0) ? "tied together" : "no connects",
 		    node2->flags);
+	 }
 	 mismatches++;
      }
+
+      nl1 = nl1->next;
   }

   // Attempt to organize devices by series and parallel combination
@@ -5923,8 +6061,11 @@ PropertyMatch(struct objlist *ob1, int file1,
   // PropertySortAndCombine can move the first property, so recompute it
   // for each circuit.

-   for (tp1 = ob1; (tp1 != NULL) && tp1->type >= FIRSTPIN; tp1 = tp1->next);
-   for (tp2 = ob2; (tp2 != NULL) && tp2->type >= FIRSTPIN; tp2 = tp2->next);
+   tp1 = tp2 = NULL;
+   if (t1type == PROPERTY)
+      for (tp1 = ob1; (tp1 != NULL) && tp1->type >= FIRSTPIN; tp1 = tp1->next);
+   if (t2type == PROPERTY)
+      for (tp2 = ob2; (tp2 != NULL) && tp2->type >= FIRSTPIN; tp2 = tp2->next);

   // Find name for printing, removing leading slash if needed.
   inst1 = ob1->instance.name;
@@ -5954,12 +6095,16 @@ PropertyMatch(struct objlist *ob1, int file1,
 	    if (vl2->type == PROP_ENDLIST) break;
 	    if (vl2 == NULL) continue;
 	    if (vl2->key == NULL) continue;
-	    kl2 = (struct property *)HashLookup(vl2->key, &(tc2->propdict));
-	    if (kl2 != NULL) {
-		// Allowed for one instance to be missing "M" or "S".
-		if (!(*matchfunc)(vl2->key, "M") && !(*matchfunc)(vl2->key, "S"))
+
+	    // Allowed for one instance to be missing "M" or "S" if the other
+	    // has value 1.
+	    if (!(*matchfunc)(vl2->key, "M") && !(*matchfunc)(vl2->key, "S")) {
+	        kl2 = (struct property *)HashLookup(vl2->key, &(tc2->propdict));
+	    	if (kl2 != NULL)
 		    break;	// Property is required
 	    }
+	    else if (vl2->value.ival != 1)
+		break;	// Property M != 1 or S != 1 is a mismatch.
 	 }
 	 if (vl2->type != PROP_ENDLIST) {
 	    mismatches++;
@@ -5990,10 +6135,12 @@ PropertyMatch(struct objlist *ob1, int file1,
      else if ((t2type != PROPERTY) && (checked_one == TRUE)) {
 	 // t1 has more property records than t2, and they did not get
 	 // merged equally by PropertySortAndCombine().
-	 Fprintf(stdout, "Circuit 2 parallel/series network does not match"
+	 if (do_print) {
+	    Fprintf(stdout, "Circuit 2 parallel/series network does not match"
 			" Circuit 1\n");
-	 DumpNetwork(ob1, 1);
-	 DumpNetwork(ob2, 2);
+	    DumpNetwork(ob1, 1);
+	    DumpNetwork(ob2, 2);
+	 }
 	 mismatches++;
      }
      else if (t2type != PROPERTY) {
@@ -6005,12 +6152,16 @@ PropertyMatch(struct objlist *ob1, int file1,
 	    if (vl1->type == PROP_ENDLIST) break;
 	    if (vl1 == NULL) continue;
 	    if (vl1->key == NULL) continue;
-	    kl1 = (struct property *)HashLookup(vl1->key, &(tc1->propdict));
-	    if (kl1 != NULL) {
-		// Allowed for one instance to be missing "M" or "S".
-		if (!(*matchfunc)(vl1->key, "M") && !(*matchfunc)(vl1->key, "S"))
+
+	    // Allowed for one instance to be missing "M" or "S" if the other
+	    // has value 1.
+	    if (!(*matchfunc)(vl1->key, "M") && !(*matchfunc)(vl1->key, "S")) {
+	        kl1 = (struct property *)HashLookup(vl1->key, &(tc1->propdict));
+	        if (kl1 != NULL)
 		    break;	// Property is required
 	    }
+	    else if (vl1->value.ival != 1)
+		break;	// Property M != 1 or S != 1 is a mismatch.
 	 }
 	 if (vl1->type != PROP_ENDLIST) {
 	    mismatches++;
@@ -6041,7 +6192,7 @@ PropertyMatch(struct objlist *ob1, int file1,
      else {
 	 int multmatch, count;
 	 PropertyCheckMismatch(tp1, tc1, inst1, tp2, tc2,
-			inst2, FALSE, FALSE, &multmatch, NULL);
+			inst2, E1, E2, FALSE, FALSE, &multmatch, NULL);
 	 if (multmatch == 1) {
 	    /* Final attempt:  Reduce M to 1 on both devices */
 	    run1 = run2 = 0;
@@ -6062,7 +6213,7 @@ PropertyMatch(struct objlist *ob1, int file1,
 	 mlist =
 #endif
 	 PropertyCheckMismatch(tp1, tc1, inst1, tp2, tc2,
-			inst2, do_print, do_list, &count, &rval);
+			inst2, E1, E2, do_print, do_list, &count, &rval);
 	 mismatches += count;
 #ifdef TCL_NETGEN
 	 if (do_list && (mlist != NULL)) {
@@ -6135,11 +6286,9 @@ PropertyCheck(struct ElementClass *EC, int do_print, int do_list, int *rval)
      E2 = Etmp;
   }
 #ifdef TCL_NETGEN
-   return PropertyMatch(E1->object, E1->graph, E2->object, E2->graph,
-		do_print, do_list, rval);
+   return PropertyMatch(E1, E2, do_print, do_list, rval);
 #else
-   PropertyMatch(E1->object, E1->graph, E2->object, E2->graph,
-		do_print, do_list, rval);
+   PropertyMatch(E1, E2, do_print, do_list, rval);
 #endif
 }

@@ -6181,7 +6330,8 @@ void PrintPropertyResults(int do_list)

 /*----------------------------------------------------------------------*/
 /* Return 0 if perfect matching found, else return number of		*/
-/* automorphisms, and return -1 if invalid matching found. 		*/
+/* automorphisms, and return -1 if invalid matching found, 		*/
+/* and return -2 if there is a port count mismatch.			*/
 /*----------------------------------------------------------------------*/

 int VerifyMatching(void)
@@ -6192,6 +6342,9 @@ int VerifyMatching(void)
  struct Element *E;
  struct Node *N;
  int C1, C2, result;
+  int P1, P2;
+  struct objlist *ob1, *ob2;
+  int portMismatch = 0;

  if (BadMatchDetected) return(-1);
  
@@ -6212,14 +6365,40 @@ int VerifyMatching(void)
    }
  }

+  P1 = P2 = 0;
  for (NC = NodeClasses; NC != NULL; NC = NC->next) {
    C1 = C2 = 0;
    for (N = NC->nodes; N != NULL; N = N->next) {
      (N->graph == Circuit1->file) ? C1++ : C2++;
+      if (IsPort(N->object)) (N->graph == Circuit1->file) ? P1++ : P2++;
    }
    if (C1 != C2) return(-1);
+    if (P1 != P2) portMismatch = 1;
    if (C1 != 1) ret++;
  }
+
+  P1 = P2 = 0;
+  if (ret == 0) {	/* automorphisms have precedence over port count mismatch */
+     if (portMismatch) return -2;
+
+     /* Count ports in each subcircuit including disconnected ports */
+     for (ob1 = Circuit1->cell; ob1 && IsPort(ob1); ob1 = ob1->next, P1++);
+     for (ob2 = Circuit2->cell; ob2 && IsPort(ob2); ob2 = ob2->next, P2++);
+     if (P1 == P2) {	// pin counts match.  Make sure disconnected pins match, too.
+	for (ob1 = Circuit1->cell; ob1 && IsPort(ob1); ob1 = ob1->next) {
+	   if (ob1->node == -1) {	// disconnected pin
+	      for (ob2 = Circuit2->cell; ob2 && IsPort(ob2); ob2 = ob2->next) {
+		 if (ob2->node == -1 && (*matchfunc)(ob1->name, ob2->name))
+		     break;	// disconnected pin match 
+	      }
+	      if (ob2 == NULL) return -2;
+	   }
+	}
+     }
+     else {	// pin count mismatch
+	return -2;
+     }
+  }
  return(ret);
 }

@@ -6280,7 +6459,7 @@ int ResolveAutomorphsByPin()
    int portnum;

    /* Diagnostic */
-    Fprintf(stdout, "Resolving automorphisms by pin name.\n");
+    Fprintf(stdout, "Resolving symmetries by pin name.\n");

    for (NC = NodeClasses; NC != NULL; NC = NC->next) {
 	struct Node *N1, *N2;
@@ -6305,6 +6484,8 @@ int ResolveAutomorphsByPin()
 		for (N2 = N1->next; N2 != NULL; N2 = N2->next) {
 		    if ((N2->graph != N1->graph) &&
 				(*matchfunc)(N2->object->name, N1->object->name)) {
+  			if (Debug == TRUE)
+			    Printf("Symmetry group broken by name match (pin %s)\n", N2->object->name);
 			Magic(newhash);
 			N1->hashval = newhash;
 			N2->hashval = newhash;
@@ -6318,7 +6499,7 @@ int ResolveAutomorphsByPin()
    FractureElementClass(&ElementClasses); 
    FractureNodeClass(&NodeClasses); 
    ExhaustiveSubdivision = 1;
-    while (!Iterate() && VerifyMatching() != -1); 
+    while (!Iterate() && VerifyMatching() >= 0); 
    return(VerifyMatching());
 }

@@ -6340,7 +6521,7 @@ int ResolveAutomorphsByProperty()
    unsigned long orighash, newhash;

    /* Diagnostic */
-    Fprintf(stdout, "Resolving automorphisms by property value.\n");
+    Fprintf(stdout, "Resolving symmetries by property value.\n");

    for (EC = ElementClasses; EC != NULL; EC = EC->next) {
 	struct Element *E1, *E2;
@@ -6378,9 +6559,10 @@ int ResolveAutomorphsByProperty()
 		badmatch = FALSE;
 		for (E2 = E1->next; E2 != NULL; E2 = E2->next) {
 		    if (E2->hashval != orighash) continue;
-		    PropertyMatch(E1->object, E1->graph, E2->object, E2->graph,
-			    FALSE, FALSE, &result);
+		    PropertyMatch(E1, E2, FALSE, FALSE, &result);
 		    if (result == 0) {
+  			if (Debug == TRUE)
+		            Printf("Symmetry group split by property (element %s)\n", E2->object->model.class);
 			E2->hashval = newhash;
 			if (E2->graph == E1->graph)
 			    C1++;
@@ -6421,7 +6603,7 @@ int ResolveAutomorphsByProperty()
    FractureElementClass(&ElementClasses); 
    FractureNodeClass(&NodeClasses); 
    ExhaustiveSubdivision = 1;
-    while (!Iterate() && VerifyMatching() != -1); 
+    while (!Iterate() && VerifyMatching() >= 0); 
    return(VerifyMatching());
 }

@@ -6447,6 +6629,7 @@ int ResolveAutomorphisms()
  struct NodeClass *NC;
  struct Node *N;
  int C1, C2;
+  int automorphs;

  for (EC = ElementClasses; EC != NULL; EC = EC->next) {
    struct Element *E1, *E2;
@@ -6498,8 +6681,9 @@ int ResolveAutomorphisms()
  FractureElementClass(&ElementClasses);
  FractureNodeClass(&NodeClasses);
  ExhaustiveSubdivision = 1;
-  while (!Iterate() && VerifyMatching() != -1);
-  return(VerifyMatching());
+  while (!Iterate() && (VerifyMatching() >= 0));
+
+  return VerifyMatching();
 }

 /*------------------------------------------------------*/
@@ -6911,7 +7095,8 @@ int EquivalenceClasses(char *name1, int file1, char *name2, int file2)
      /* conflicting names exist, then alter the classhash to make it	*/
      /* unique.  In the case of duplicate cells, don't do this.	*/

-      if (!(tp->flags & CELL_DUPLICATE) && !(tp2->flags & CELL_DUPLICATE)) {
+      if (!(tp->flags & CELL_DUPLICATE) && !(tp2->flags & CELL_DUPLICATE) &&
+			!(*matchfunc)(name1, name2)) {
 	 tpx = LookupCellFile(name1, file2);
 	 if (tpx != NULL) need_new_seed = 1;
 	 tpx = LookupCellFile(name2, file1);
@@ -7193,37 +7378,36 @@ struct nlist *addproxies(struct hashlist *p, void *clientdata)
    return NULL;	/* Keep the search going */
 }

-/*------------------------------------------------------*/
-/* Declare that the device class "name1" is equivalent	*/
-/* to class "name2".  This is the same as the above	*/
-/* routine, except that the cells must be at the top	*/
-/* of the compare queue, and must already be proven	*/
-/* equivalent by LVS.  Determine a pin correspondence,	*/
-/* then modify all instances of "name2" to match all	*/
-/* instances of "name1" by pin reordering.  If either	*/
-/* cell has disconnected pins, they are shuffled to the	*/
-/* end of the pin list.  If two or more pins correspond	*/
-/* to net automorphisms, then they are added to the	*/
-/* list of permuted pins.				*/
-/*							*/
-/* NOTE:  This routine must not be called on any	*/
-/* circuit pair that has not been matched.  If a 	*/
-/* circuit pair has been matched with automorphisms,	*/
-/* then some pins may be matched arbitrarily.		*/
-/*							*/
-/* If "dolist" is 1, append the list representing the	*/
-/* output (if any) to variable tcl_out, if it exists.	*/
-/*							*/
-/* Return codes:					*/
-/* 2: Neither cell had pins, so matching is unnecessary	*/
-/* 1: Exact match					*/
-/* 0: Inexact match resolved by proxy pin insertion	*/
-/*------------------------------------------------------*/
+/*--------------------------------------------------------------*/
+/* Declare that the device class "name1" is equivalent to class	*/
+/* "name2".  This is the same as the above routine, except that	*/
+/* the cells must be at the top	of the compare queue, and must	*/
+/* already be proven equivalent by LVS.  Determine a pin	*/
+/* correspondence, then modify all instances of "name2" to	*/
+/* match all instances of "name1" by pin reordering.  If either	*/
+/* cell has disconnected pins, they are shuffled to the	end of	*/
+/* the pin list.  If two or more pins correspond to net		*/
+/* automorphisms, then they are added to the list of permuted	*/
+/* pins.							*/
+/*								*/
+/* NOTE:  This routine must not be called on any circuit pair	*/
+/* that has not been matched.  If a circuit pair has been	*/
+/* matched with automorphisms, then some pins may be matched	*/
+/* arbitrarily.							*/
+/*								*/
+/* If "dolist" is 1, append the list representing the output	*/
+/* (if any) to variable tcl_out, if it exists.			*/
+/*								*/
+/* Return codes:						*/
+/*  2: Neither cell had pins, so matching is unnecessary	*/
+/*  1: Exact match						*/
+/*  0: Inexact match resolved by proxy pin insertion.		*/
+/*--------------------------------------------------------------*/

 int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
 {
   char *cover, *ctemp;
-   char *bangptr1, *bangptr2;
+   char *bangptr1, *bangptr2, *backslashptr1, *backslashptr2;
   struct objlist *ob1, *ob2, *obn, *obp, *ob1s, *ob2s, *obt;
   struct NodeClass *NC;
   struct Node *N1, *N2;
@@ -7297,8 +7481,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
 	    if (IsPort(obn)) {
 	       i = 0;
 	       for (ob1 = tc1->cell; ob1 != NULL; ob1 = ob1->next, i++) {
-	          if ((IsPort(ob1))
-				&& (*matchfunc)(ob1->name, obn->name)) {
+	          if ((IsPort(ob1)) && (ob1->node == obn->node)) {
 		     b = 0;
                     for (N2 = NC->nodes; N2 != NULL; N2 = N2->next) {
 	                if (N2->graph != Circuit1->file) {
@@ -7323,20 +7506,41 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
 		     obp = N2->object;
 		     j = 0;
 	             for (ob2 = tc2->cell; ob2 != NULL; ob2 = ob2->next, j++) {
-	                if ((IsPort(ob2))
-					&& (*matchfunc)(ob2->name, obp->name)) {
+	          	if ((IsPort(ob2)) && (ob2->node == obp->node)) {
 			   if (Debug == 0) {
 			      for (m = 0; m < left_col_end; m++) *(ostr + m) = ' ';
 			      for (m = left_col_end + 1; m < right_col_end; m++) *(ostr + m) = ' ';
-			      snprintf(ostr, left_col_end, "%s", obn->name);
-			      if ((*matchfunc)(obn->name, obp->name))
-			         snprintf(ostr + left_col_end + 1, left_col_end, "%s", obp->name);
+			      snprintf(ostr, left_col_end, "%s", ob1->name);
+			      if ((*matchfunc)(ob1->name, ob2->name))
+			         snprintf(ostr + left_col_end + 1, left_col_end, "%s", ob2->name);
 			      else {
-			         snprintf(ostr + left_col_end + 1, left_col_end, "%s **Mismatch**", obp->name);
-				 /* Pins with different names are on different nets,
-				  * so this should trigger an error return code.
+				 /* Check remainder of ports to see if there is a name match on the
+				  * same net number (multiple ports tied to the same net)
 				  */
-				 result = 0;
+				 struct objlist *ob3;
+				 for (ob3 = ob2->next, ++j; ob3 != NULL; ob3 = ob3->next, j++) {
+				     if ((IsPort(ob3)) && (ob3->node == ob2->node)) {
+					if ((*matchfunc)(ob3->name, ob1->name)) {
+					   ob2 = ob3;
+			         	   snprintf(ostr + left_col_end + 1, left_col_end, "%s", ob2->name);
+					   break;
+					}
+				     }
+				     else {
+					ob3 = NULL;
+					break;	/* All pins w/the same node should be together */
+				     }
+				 }
+				 if (ob3 == NULL) {
+				    if (ob2->model.port == -1)
+				       snprintf(ostr + left_col_end + 1, left_col_end, "%s **Mismatch**", ob2->name);
+				    else
+				       snprintf(ostr + left_col_end + 1, left_col_end, "(no matching pin)");
+				    /* Pins with different names are on different nets,
+				     * so this should trigger an error return code.
+				     */
+				    result = 0;
+				 }
 			      }
 			      for (m = 0; m < right_col_end + 1; m++)
 				 if (*(ostr + m) == '\0') *(ostr + m) = ' ';
@@ -7358,7 +7562,16 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
 #endif
 			   ob2->model.port = i;		/* save order */
 			   *(cover + i) = (char)1;
-			   break;
+
+			   /* If there are multiple pins on the same net, cycle through them;	*/
+			   /* otherwise, move to the next entry in the partition.		*/
+			   if (ob1->next && (ob1->next->type == PORT) && (ob1->next->node == ob1->node)) {
+			      ob1 = ob1->next;
+			      ob2 = tc2->cell;	/* Restart search for matching pin */
+			      i++;
+			   }
+			   else
+			      break;
 			}
 		     }
 		     if (ob2 == NULL) {
@@ -7449,14 +7662,21 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
   /* This should not happen if unconnected pins are eliminated	*/
   /* so apply only to black-box (CELL_PLACEHOLDER) entries.	*/ 
   /* (Semi-hack: Allow "!" global flag) */
+   /* (Another semi-hack: Ignore the leading backslash in	*/
+   /* backslash-escaped verilog names.  Removing the backslash	*/
+   /* and ending space character is a common way to convert to	*/
+   /* legal SPICE.						*/

   ob1 = tc1->cell;
-   bangptr1 = strrchr(ob1->name, '!');
-   if (bangptr1 && (*(bangptr1 + 1) == '\0'))
-      *bangptr1 = '\0';
-   else bangptr1 = NULL;
  
   for (i = 0; i < numorig; i++) {
+      bangptr1 = strrchr(ob1->name, '!');
+      if (bangptr1 && (*(bangptr1 + 1) == '\0'))
+         *bangptr1 = '\0';
+      else bangptr1 = NULL;
+
+      backslashptr1 = (*(ob1->name) == '\\') ? ob1->name + 1 : ob1->name;
+
      if (*(cover + i) == (char)0) {
 	 j = 0;
         for (ob2 = tc2->cell; ob2 != NULL; ob2 = ob2->next) {
@@ -7469,8 +7689,10 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
 	       *bangptr2 = '\0';
 	    else bangptr2 = NULL;

-	    name1 = ob1->name;
-	    name2 = ob2->name;
+   	    backslashptr2 = (*(ob2->name) == '\\') ? ob2->name + 1 : ob2->name;
+
+	    name1 = backslashptr1;
+	    name2 = backslashptr2;

 	    /* Recognize proxy pins as matching unconnected pins */
 	    if (!strncmp(name1, "proxy", 5) && (ob2->node == -1)) name1 +=5;
@@ -7775,7 +7997,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
   }

   /* Check for ports that did not get ordered */
-   for (obn = tc2->cell; obn && (obn->type == PORT); obn = obn->next) {
+   for (obn = tc2->cell; obn && IsPort(obn); obn = obn->next) {
      if (obn->model.port == -1) {
 	 if (obn->node == -1) {
 	    // This only happens when pins have become separated from any net.
@@ -7953,10 +8175,12 @@ int EquivalentElement(char *name, struct nlist *circuit, struct objlist **retobj
 void FlattenCurrent()
 {
   if (Circuit1 != NULL && Circuit2 != NULL) {
-      Fprintf(stdout, "Flattening subcell %s\n", Circuit1->name);
+      Fprintf(stdout, "Flattening subcell %s (%d)\n", Circuit1->name,
+		Circuit1->file);
      FlattenInstancesOf(Circuit1->name, Circuit1->file);

-      Fprintf(stdout, "Flattening subcell %s\n", Circuit2->name);
+      Fprintf(stdout, "Flattening subcell %s (%d)\n", Circuit2->name,
+		Circuit2->file);
      FlattenInstancesOf(Circuit2->name, Circuit2->file);
   }
 }
@@ -8027,7 +8251,25 @@ int Compare(char *cell1, char *cell2)
    PrintIllegalClasses();
    return(0);
  }
-  if (automorphisms == 0) Fprintf(stdout, "Circuits match correctly.\n");
+
+  if (automorphisms > 0) {
+     Fprintf(stdout, "Circuits match with %d symmetries.\n", automorphisms);
+     if (VerboseOutput) PrintAutomorphisms();
+
+     /* arbitrarily resolve automorphisms */
+     Fprintf(stdout, "\n");
+     Fprintf(stdout, "Resolving symmetries by arbitrary symmetry breaking:\n");
+     while ((automorphisms = ResolveAutomorphisms()) > 0) ;
+     if (automorphisms == -1) {
+	MatchFail(cell1, cell2);
+	Fprintf(stdout, "Circuits do not match.\n");
+	return 0;
+     }
+  }
+  if (automorphisms == -2) {	// Port count mismatch
+     Fprintf(stderr, "Port counts do not match.\n");
+     return 0;
+  }
  if (PropertyErrorDetected == 1) {
     Fprintf(stdout, "There were property errors.\n");
     PrintPropertyResults(0);
@@ -8036,30 +8278,18 @@ int Compare(char *cell1, char *cell2)
     Fprintf(stdout, "There were missing properties.\n");
     PrintPropertyResults(0);
  }
-  if (automorphisms == 0) return(1);
+  else
+     Fprintf(stdout, "Circuits match correctly.\n");

-  Fprintf(stdout, "Circuits match with %d automorphisms.\n", automorphisms);
-  if (VerboseOutput) PrintAutomorphisms();
-
-  /* arbitrarily resolve automorphisms */
-  Fprintf(stdout, "\n");
-  Fprintf(stdout, "Resolving automorphisms by arbitrary symmetry breaking:\n");
-  while ((automorphisms = ResolveAutomorphisms()) > 0) ;
-  if (automorphisms == -1) {
-    MatchFail(cell1, cell2);
-    Fprintf(stdout, "Circuits do not match.\n");
-    return(0);
-  }
-  Fprintf(stdout, "Circuits match correctly.\n");
-  return(1);
+  return 1;
 }


 void NETCOMP(void)
 /* a simple command interpreter to manage embedding/routing */
 {
-  char name[100];
-  char name2[100];
+  char name[MAX_STR_LEN];
+  char name2[MAX_STR_LEN];
  char ch;
  
  setjmp(jmpenv);
@@ -8105,9 +8335,12 @@ void NETCOMP(void)
 	  PrintIllegalClasses();
 	  Fprintf(stdout, "Netlists do not match.\n");
 	}
+	else if (automorphisms == -2) {		// port count mismatch
+	   Fprintf(stdout, "Port counts do not match.\n");
+	}
 	else {
 	  if (automorphisms) 
-	    Printf("Circuits match with %d automorphisms.\n", automorphisms);
+	    Printf("Circuits match with %d symmetries.\n", automorphisms);
 	  else Printf("Circuits match correctly.\n");
 	}
      }
@@ -8120,11 +8353,13 @@ void NETCOMP(void)
 	while (!Iterate()) ; 
 	automorphisms = VerifyMatching();
 	if (automorphisms == -1) Fprintf(stdout, "Netlists do not match.\n");
+	else if (automorphisms == -2) Fprintf(stdout, "Port counts do not match.\n");
 	else {
-	  Printf("Netlists match with %d automorphisms.\n", automorphisms);
+	  Printf("Netlists match with %d symmetries.\n", automorphisms);
 	  while ((automorphisms = ResolveAutomorphisms()) > 0)
-	    Printf("  automorphisms = %d.\n", automorphisms);
+	    Printf("  symmetries = %d.\n", automorphisms);
 	  if (automorphisms == -1) Fprintf(stdout, "Netlists do not match.\n");
+	  else if (automorphisms == -2) Fprintf(stdout, "Port counts do not match.\n");
 	  else Printf("Circuits match correctly.\n");
 	}
      }
@@ -8152,7 +8387,7 @@ void NETCOMP(void)
      break;
    case 'p':
      {
-	char model[100];
+	char model[MAX_STR_LEN];
 	/* equivalence two pins on a given class of element */
 	Printf("Allow permutation of two pins.\n");
 	promptstring("Enter cellname: ",model);
@@ -8189,7 +8424,7 @@ void NETCOMP(void)
      Printf("(c)reate internal data structure\n");
      Printf("do an (i)teration\n");
      Printf("(r)un to completion (convergence)\n");
-      Printf("(R)un to completion (resolve automorphisms)\n");
+      Printf("(R)un to completion (resolve symmetries)\n");
      Printf("(v)erify results\n");
      Printf("print (a)utomorphisms\n");
      Printf("equate two (d)evices\n");
@@ -914,7 +914,7 @@ char *ReadNetlist(char *fname, int *fnum)
  }
  /* try appending extensions in sequence, and testing for file existance */
  for (index = 0; formats[index].extension != NULL; index++) {
-    char testname[200];
+    char testname[MAX_STR_LEN];
    strcpy(testname, fname);
    strcat(testname, formats[index].extension);
    if (OpenParseFile(testname, *fnum) >= 0) {
@@ -1019,7 +1019,7 @@ void WriteNetgenFile(char *name, char *filename)

 char *ReadNetgenFile (char *fname, int *fnum)
 {
-  char name[100];
+  char name[MAX_STR_LEN];
  char *LastCellRead = NULL;
  int filenum;

@@ -1255,7 +1255,7 @@ int READ(void *buf, int bytes)

 char *ReadNetgenFile (char *fname, int *fnum)
 {
-  char name[100];
+  char name[MAX_STR_LEN];
  int len, chars;
  char *LastCellRead = NULL;

@@ -57,7 +57,7 @@ int AddToExistingDefinition = 0;  /* default: overwrite cell when reopened */
 extern int errno;	/* Defined in stdlib.h */

 #define MAX_STATIC_STRINGS 5
-static char staticstrings[MAX_STATIC_STRINGS][200];
+static char staticstrings[MAX_STATIC_STRINGS][MAX_STR_LEN];
 static int laststring;

 extern struct hashdict spiceparams;	/* From spice.c */
@@ -984,6 +984,51 @@ PropertyDelete(char *name, int fnum, char *key)
    return 0;
 }

+/*----------------------------------------------------------------------*/
+/* Associate a property with a specific pin				*/
+/*----------------------------------------------------------------------*/
+
+int
+PropertyAssociatePin(char *name, int fnum, char *key, char *pin)
+{
+    struct property *kl = NULL;
+    struct nlist *tc;
+    struct objlist *ob;
+    int result;
+
+    if ((fnum == -1) && (Circuit1 != NULL) && (Circuit2 != NULL)) {
+	result = PropertyAssociatePin(name, Circuit1->file, key, pin);
+	result = PropertyAssociatePin(name, Circuit2->file, key, pin);
+	return result;
+    }
+
+    tc = LookupCellFile(name, fnum);
+    if (tc == NULL) {
+	Printf("No device %s found for PropertyAssociatePin()\n", name);
+	return -1;
+    }
+
+    kl = (struct property *)HashLookup(key, &(tc->propdict));
+    if (kl == NULL) {
+	Printf("No property %s found for device %s\n", key, name);
+	return -1;
+    }
+    else {
+        for (ob = tc->cell; ob != NULL; ob = ob->next) {
+	    if (ob->type != PORT) break;
+	    else if ((*matchfunc)(ob->name, pin)) {
+		kl->pin = ob->name;
+		break;
+	    }
+        }
+	if (ob == NULL) {
+	    Printf("No pin %s found for device %s\n", pin, name);
+	    return -1;
+	}
+    }
+    return 0;
+}
+
 /*----------------------------------------------------------------------*/
 /* Set the tolerance of a property in the master cell record.		*/
 /*----------------------------------------------------------------------*/
@@ -39,6 +39,7 @@ extern void SetParallelCombine(int value);
 extern void SetSeriesCombine(int value);
 extern int  PropertyTolerance(char *name, int fnum, char *key, int ival,
 		double dval);
+extern int  PropertyAssociatePin(char *name, int fnum, char *key, char *pin);
 extern int  PropertyMerge(char *name, int fnum, char *key, int merge_type,
 		int merge_mask);
 extern void ResolveProperties(char *name1, int file1, char *name2, int file2);
@@ -181,7 +181,7 @@ void Ntk(char *name, char *filename)

 char *ReadNtk (char *fname, int *fnum)
 {
-  char	model[100], instancename[100], name[100];
+  char	model[MAX_STR_LEN], instancename[MAX_STR_LEN], name[MAX_STR_LEN];
  struct objlist *ob;
  int CellDefInProgress = 0;
  int filenum;
@@ -218,7 +218,7 @@ char *ReadNtk (char *fname, int *fnum)
      }
    } 
    else if (match(nexttok, "s")) {
-      char last[100];
+      char last[MAX_STR_LEN];
      *last = '\0';
      if (!CellDefInProgress) {
 	/* fake cell declaration for top-level call */
@@ -130,6 +130,7 @@ struct property *NewProperty(void)
 	
 	kl = (struct property *)CALLOC(1,sizeof(struct property));
 	if (kl == NULL) Fprintf(stderr,"NewProperty: Core allocation error\n");
+	kl->pin = (char *)NULL;
 	return (kl);
 }

@@ -440,15 +441,32 @@ void RemoveShorted(char *class, int file)
   RecurseCellFileHashTable(removeshorted, file);
 }

+/* Remove instances of a deleted class from the database.	*/
+/* NOTE:  This treats deleted classes as not existing, so it	*/
+/* needs to take care of disconnected ports in the same manner	*/
+/* as flattenInstancesOf() in disconnecting the port of a	*/
+/* parent cell if it connected to nothing other than the	*/
+/* deleted instance.						*/
+
 int deleteclass(struct hashlist *p, int file)
 {
   struct nlist *ptr;
-   struct objlist *ob, *lob, *nob;
+   struct objlist *ob, *lob, *nob, *portnode;
+   unsigned char *checknodes;
+   int i;

   ptr = (struct nlist *)(p->ptr);

   if ((file != -1) && (ptr->file != file)) return 0;

+   /* Note:  This could be made faster by enumerating all times each
+    * node is used during the full pass, then subtracting each time
+    * the node is deleted in a child, then disconnecting all nodes
+    * that ended up with a zero count.
+    */
+   checknodes = (unsigned char *)CALLOC(ptr->nodename_cache_maxnodenum + 1,
+		sizeof(unsigned char));
+
   lob = NULL;
   for (ob = ptr->cell; ob != NULL;) {
      nob = ob->next;
@@ -456,6 +474,8 @@ int deleteclass(struct hashlist *p, int file)
 	 if ((*matchfunc)(ob->model.class, OldCell->name)) {
 	    HashDelete(ob->instance.name, &(ptr->instdict));
 	    while (1) {
+	       if (ob->type >= FIRSTPIN)
+		  checknodes[ob->node] = (unsigned char)1;
 	       FreeObjectAndHash(ob, ptr);
 	       ob = nob;
 	       if (ob == NULL) break;
@@ -477,6 +497,25 @@ int deleteclass(struct hashlist *p, int file)
         ob = nob;
      }
   }
+
+   for (i = 0; i <= ptr->nodename_cache_maxnodenum; i++) {
+      if (checknodes[i] != 0) {
+         portnode = NULL;
+         for (ob = ptr->cell; ob != NULL; ob = ob->next) {
+	    if ((ob->type != PORT) && (portnode == NULL))
+	       break;
+	    else if ((ob->type == PORT) && (ob->node == i))
+	       portnode = ob;
+	    else if ((ob->type >= FIRSTPIN) && (ob->node == i))
+	       break;
+         }
+         if ((ob == NULL) && (portnode != NULL)) {
+	    /* Port became disconnected when child was deleted */
+	    portnode->node = -1;
+         }
+      }
+   }
+   FREE(checknodes);
 }

 /* Remove all instances of class "class" from the database */
@@ -697,7 +736,7 @@ struct nlist *RecurseCellHashTable2(struct nlist *(*foo)(struct hashlist *,
 		
 char *FixTemplate(char *t)
 {
-	char buffer[200];
+	char buffer[MAX_STR_LEN];
 	char *rstr;
 	int i,j;
 	int InsideBrace;
@@ -1208,7 +1247,7 @@ static char *OldNodeName(struct nlist *tp, int node)
  struct objlist *firstuniqueglobal;
  struct objlist *firstglobal;
  struct objlist *firstpin;
-  static char StrBuffer[100];
+  static char StrBuffer[MAX_STR_LEN];

 #if 0
  /* make second pass, looking for ports */
@@ -135,6 +135,7 @@ struct property {
  unsigned char idx;		/* index into valuelist */
  unsigned char type;		/* string, integer, double, value, expression */
  unsigned char merge;		/* how property changes when devices are merged */
+  char *pin;			/* associated pin (or NULL if not associated)	*/
  union {
     char *string;
     double dval;
@@ -206,7 +207,7 @@ struct nlist {
  char *name;
  int number;		/* number of instances defined */
  int dumped;		/* instance count, and general-purpose marker */
-  unsigned char flags;
+  unsigned short flags;
  unsigned char class;
  unsigned long classhash;	/* randomized hash value for cell class */
  struct Permutation *permutes;	/* list of permuting pins */
@@ -222,17 +223,18 @@ struct nlist {

 /* Defined nlist structure flags */

-#define CELL_MATCHED		0x01	/* cell matched to another */
-#define CELL_NOCASE		0x02	/* cell is case-insensitive (e.g., SPICE) */
-#define CELL_TOP		0x04	/* cell is a top-level cell */
-#define CELL_PLACEHOLDER	0x08	/* cell is a placeholder cell */
-#define CELL_PROPSMATCHED	0x10	/* properties matched to matching cell */
-#define CELL_DUPLICATE		0x20	/* cell has a duplicate */
+#define CELL_MATCHED		0x001	/* cell matched to another */
+#define CELL_NOCASE		0x002	/* cell is case-insensitive (e.g., SPICE) */
+#define CELL_TOP		0x004	/* cell is a top-level cell */
+#define CELL_PLACEHOLDER	0x008	/* cell is a placeholder cell */
+#define CELL_PROPSMATCHED	0x010	/* properties matched to matching cell */
+#define CELL_DUPLICATE		0x020	/* cell has a duplicate */
+#define CELL_VERILOG		0x040	/* cell is verilog module */

 /* Flags for combination allowances and prohibitions */

-#define COMB_SERIES		0x40
-#define COMB_NO_PARALLEL	0x80
+#define COMB_SERIES		0x100
+#define COMB_NO_PARALLEL	0x200

 extern struct nlist *CurrentCell;
 extern struct objlist *CurrentTail;
@@ -511,8 +511,8 @@ int OpenEmbeddingFile(char *cellname, char *filename)
 /* returns 1 if OK */
 {
  struct nlist *tp;
-  char outfilename[200];
-  char logfilename[200];
+  char outfilename[MAX_STR_LEN];
+  char logfilename[MAX_STR_LEN];

  tp = LookupCell(cellname);
  if (tp == NULL) {
@@ -783,7 +783,7 @@ void SetupArray(char *prompt1, char *prompt2, char *prompt3, int *data,
                void (*proc)(void))
 {
  int i, oldfanout;
-  char name[100];
+  char name[MAX_STR_LEN];

  Printf(prompt1);
  for (i = 1; i <= MAX_TREE_DEPTH; i++) 
@@ -792,7 +792,7 @@ void SetupArray(char *prompt1, char *prompt2, char *prompt3, int *data,

  oldfanout = 1;
  for (i = 1; i <= MAX_TREE_DEPTH; i++) {
-    char prompt[100];
+    char prompt[MAX_STR_LEN];
    int newfanout;
    sprintf(prompt, prompt2, i);
    promptstring(prompt, name);
@@ -822,7 +822,7 @@ void SetupArrayFromString(char *prompt1, char *prompt3, int *data,
                void (*proc)(void), char *text)
 {
  int i, oldfanout, newfanout;
-  char string[100];
+  char string[MAX_STR_LEN];
  char *ch;
  char *endch;

@@ -962,7 +962,7 @@ void ProtoPrintParameters(void)
 void PROTOCHIP(void)
 /* a simple command interpreter to manage embedding/routing */
 {
-  char name[100];
+  char name[MAX_STR_LEN];
  char ch;
  
  InitializeFanout();
@@ -1136,7 +1136,7 @@ void PROTOCHIP(void)

      oldfanout = 1;
      for (i = 1; i <= MAX_TREE_DEPTH; i++) {
-	char prompt[100];
+	char prompt[MAX_STR_LEN];
 	int newfanout;
 	sprintf(prompt,"Fanout for level %d (0 to quit): ",i);
 	promptstring(prompt, name);
@@ -1168,7 +1168,7 @@ void PROTOCHIP(void)

      oldfanout = 1;
      for (i = 1; i <= MAX_TREE_DEPTH; i++) {
-	char prompt[100];
+	char prompt[MAX_STR_LEN];
 	int newfanout;
 	sprintf(prompt,"Common nodes for level %d (0 to quit): ",i);
 	promptstring(prompt, name);
@@ -1200,7 +1200,7 @@ void PROTOCHIP(void)

      oldfanout = 1;
      for (i = 1; i <= MAX_TREE_DEPTH; i++) {
-	char prompt[100];
+	char prompt[MAX_STR_LEN];
 	int newfanout;
 	sprintf(prompt,"Used leaves for level %d (0 to quit): ",i);
 	promptstring(prompt, name);
@@ -37,7 +37,7 @@ extern int ColumnBase;

 struct filestr {
  FILE *f;
-  char buffer[200];
+  char buffer[MAX_STR_LEN];
  int wrap;  /* column to wrap around in, or 0 if no wrap */
 } file_buffers[MAXFILES];

@@ -107,7 +107,7 @@ void Fprintf(FILE *f, char *format, ...)
 {
  va_list ap;
  int FileIndex;
-  char tmpstr[200];
+  char tmpstr[MAX_STR_LEN];
  int bufferlongenough;
  int linewrapexceeded;

@@ -203,7 +203,7 @@ void Printf(char *format, ...)
 void Printf(char *format, ...)
 {
  va_list ap;
-  char tmpstr[200];
+  char tmpstr[MAX_STR_LEN];

  va_start(ap, format);
  vsprintf(tmpstr, format, ap);
@@ -52,7 +52,7 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 /*************************************************************************/

 static int SuppressPrompts = 0;
-static char InputLine[200];
+static char InputLine[MAX_STR_LEN];

 void typeahead(char *str)
 {
@@ -73,7 +73,7 @@ but reads from 'promptstring_infile' if nec. */
 /* If interactive, puts out 'prompt' */
 {
  char *nexttok;
-  char tmpstr[200];
+  char tmpstr[MAX_STR_LEN];
  int echo;

  if (promptstring_infile == NULL)
@@ -959,8 +959,8 @@ void Query(void)
 {
  /* little interactive debugger */
  char reply;
-  char repstr[100];
-  char repstr2[100];
+  char repstr[MAX_STR_LEN];
+  char repstr2[MAX_STR_LEN];
  float StartTime;   /* for elapsed CPU times */
  int Timing;  /* if true, print times of each command */
  int filenum = -1;
@@ -518,13 +518,13 @@ void ReadSpiceFile(char *fname, int filenum, struct cellstack **CellStackPtr,
  int warnings = 0, update = 0, hasports = 0;
  char *eqptr, devtype, in_subckt;
  struct keyvalue *kvlist = NULL;
-  char inst[256], model[256], instname[256];
+  char inst[MAX_STR_LEN], model[MAX_STR_LEN], instname[MAX_STR_LEN];
  struct nlist *tp;
  struct objlist *parent, *sobj, *nobj, *lobj, *pobj;

-  inst[255] = '\0';
-  model[255] = '\0';
-  instname[255] = '\0';
+  inst[MAX_STR_LEN-1] = '\0';
+  model[MAX_STR_LEN-1] = '\0';
+  instname[MAX_STR_LEN-1] = '\0';
  in_subckt = (char)0;
  
  while (!EndParseFile()) {
@@ -555,7 +555,7 @@ void ReadSpiceFile(char *fname, int filenum, struct cellstack **CellStackPtr,

      /* Check for existence of the cell.  We may need to rename it. */

-      snprintf(model, 99, "%s", nexttok);
+      snprintf(model, MAX_STR_LEN-1, "%s", nexttok);
      tp = LookupCellFile(nexttok, filenum);

      /* Check for name conflict with duplicate cell names	*/
@@ -703,7 +703,7 @@ skip_ends:

      SpiceTokNoNewline();
      if (nexttok == NULL) continue;	/* Ignore if no model name */
-      snprintf(model, 99, "%s", nexttok);
+      snprintf(model, MAX_STR_LEN-1, "%s", nexttok);
      SpiceTokNoNewline();
      if (nexttok == NULL) goto baddevice;

@@ -887,29 +887,29 @@ skip_ends:
    }

    else if (toupper(nexttok[0]) == 'Q') {
-      char emitter[100], base[100], collector[100];
-      emitter[99] = '\0';
-      base[99] = '\0';
-      collector[99] = '\0';
+      char emitter[MAX_STR_LEN], base[MAX_STR_LEN], collector[MAX_STR_LEN];
+      emitter[MAX_STR_LEN-1] = '\0';
+      base[MAX_STR_LEN-1] = '\0';
+      collector[MAX_STR_LEN-1] = '\0';

      if (!(*CellStackPtr)) {
 	CellDef(fname, filenum);
 	PushStack(fname, CellStackPtr);
      }
-      strncpy(inst, nexttok + 1, 99); SpiceTokNoNewline(); 
+      strncpy(inst, nexttok + 1, MAX_STR_LEN-1); SpiceTokNoNewline(); 
      if (nexttok == NULL) goto baddevice;
-      strncpy(collector, nexttok, 99); SpiceTokNoNewline();
+      strncpy(collector, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
      if (nexttok == NULL) goto baddevice;
-      strncpy(base, nexttok, 99);   SpiceTokNoNewline();
+      strncpy(base, nexttok, MAX_STR_LEN-1);   SpiceTokNoNewline();
      if (nexttok == NULL) goto baddevice;
-      strncpy(emitter, nexttok, 99);  SpiceTokNoNewline();
+      strncpy(emitter, nexttok, MAX_STR_LEN-1);  SpiceTokNoNewline();
      /* make sure all the nodes exist */
      if (LookupObject(collector, CurrentCell) == NULL) Node(collector);
      if (LookupObject(base, CurrentCell) == NULL) Node(base);
      if (LookupObject(emitter, CurrentCell) == NULL) Node(emitter);

      /* Read the device model */
-      snprintf(model, 99, "%s", nexttok);
+      snprintf(model, MAX_STR_LEN-1, "%s", nexttok);

      while (nexttok != NULL)
      {
@@ -940,30 +940,30 @@ skip_ends:
 	 goto baddevice;
      }

-      snprintf(instname, 255, "%s:%s", model, inst);
+      snprintf(instname, MAX_STR_LEN-1, "%s:%s", model, inst);
      Cell(instname, model, collector, base, emitter);
      pobj = LinkProperties(model, kvlist);
      ReduceExpressions(pobj, NULL, CurrentCell, TRUE);
      DeleteProperties(&kvlist);
    }
    else if (toupper(nexttok[0]) == 'M') {
-      char drain[100], gate[100], source[100], bulk[100];
-      drain[99] = '\0';
-      gate[99] = '\0';
-      source[99] = '\0';
-      bulk[99] = '\0';
+      char drain[MAX_STR_LEN], gate[MAX_STR_LEN], source[MAX_STR_LEN], bulk[MAX_STR_LEN];
+      drain[MAX_STR_LEN-1] = '\0';
+      gate[MAX_STR_LEN-1] = '\0';
+      source[MAX_STR_LEN-1] = '\0';
+      bulk[MAX_STR_LEN-1] = '\0';

      if (!(*CellStackPtr)) {
 	CellDef(fname, filenum);
 	PushStack(fname, CellStackPtr);
      }
-      strncpy(inst, nexttok + 1, 99); SpiceTokNoNewline(); 
+      strncpy(inst, nexttok + 1, MAX_STR_LEN-1); SpiceTokNoNewline(); 
      if (nexttok == NULL) goto baddevice;
-      strncpy(drain, nexttok, 99);  SpiceTokNoNewline();
+      strncpy(drain, nexttok, MAX_STR_LEN-1);  SpiceTokNoNewline();
      if (nexttok == NULL) goto baddevice;
-      strncpy(gate, nexttok, 99);   SpiceTokNoNewline();
+      strncpy(gate, nexttok, MAX_STR_LEN-1);   SpiceTokNoNewline();
      if (nexttok == NULL) goto baddevice;
-      strncpy(source, nexttok, 99); SpiceTokNoNewline();
+      strncpy(source, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
      if (nexttok == NULL) goto baddevice;
      /* make sure all the nodes exist */
      if (LookupObject(drain, CurrentCell) == NULL) Node(drain);
@@ -971,11 +971,11 @@ skip_ends:
      if (LookupObject(source, CurrentCell) == NULL) Node(source);

      /* handle the substrate node */
-      strncpy(bulk, nexttok, 99); SpiceTokNoNewline();
+      strncpy(bulk, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
      if (LookupObject(bulk, CurrentCell) == NULL) Node(bulk);

      /* Read the device model */
-      snprintf(model, 99, "%s", nexttok);
+      snprintf(model, MAX_STR_LEN-1, "%s", nexttok);

      while (nexttok != NULL)
      {
@@ -1013,7 +1013,7 @@ skip_ends:
 	 goto baddevice;
      }

-      snprintf(instname, 255, "%s:%s", model, inst);
+      snprintf(instname, MAX_STR_LEN-1, "%s:%s", model, inst);
      Cell(instname, model, drain, gate, source, bulk);
      pobj = LinkProperties(model, kvlist);
      ReduceExpressions(pobj, NULL, CurrentCell, TRUE);
@@ -1027,19 +1027,19 @@ skip_ends:
 	 SpiceSkipNewLine();
      }
      else {
-        char ctop[100], cbot[100];
-        ctop[99] = '\0';
-        cbot[99] = '\0';
+        char ctop[MAX_STR_LEN], cbot[MAX_STR_LEN];
+        ctop[MAX_STR_LEN-1] = '\0';
+        cbot[MAX_STR_LEN-1] = '\0';

        if (!(*CellStackPtr)) {
 	  CellDef(fname, filenum);
 	  PushStack(fname, CellStackPtr);
        }
-        strncpy(inst, nexttok + 1, 99); SpiceTokNoNewline(); 
+        strncpy(inst, nexttok + 1, MAX_STR_LEN-1); SpiceTokNoNewline(); 
        if (nexttok == NULL) goto baddevice;
-        strncpy(ctop, nexttok, 99); SpiceTokNoNewline();
+        strncpy(ctop, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
        if (nexttok == NULL) goto baddevice;
-        strncpy(cbot, nexttok, 99); SpiceTokNoNewline();
+        strncpy(cbot, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();

        /* make sure all the nodes exist */
        if (LookupObject(ctop, CurrentCell) == NULL) Node(ctop);
@@ -1058,7 +1058,7 @@ skip_ends:

 	model[0] = '\0';
 	if ((nexttok != NULL) && ((eqptr = strchr(nexttok, '=')) == NULL))
-	   snprintf(model, 99, "%s", nexttok);
+	   snprintf(model, MAX_STR_LEN-1, "%s", nexttok);

 	/* Any other device properties? */
        while (nexttok != NULL)
@@ -1071,7 +1071,7 @@ skip_ends:
 	   }
 	   else if (!strncmp(nexttok, "$[", 2)) {
 	      // Support for CDL modeled capacitor format
-	      snprintf(model, 99, "%s", nexttok + 2);
+	      snprintf(model, MAX_STR_LEN-1, "%s", nexttok + 2);
 	      if ((eqptr = strchr(model, ']')) != NULL)
 		 *eqptr = '\0';
 	   }
@@ -1104,7 +1104,7 @@ skip_ends:
 	   usemodel = 1;
 	}

-	snprintf(instname, 255, "%s:%s", model, inst);
+	snprintf(instname, MAX_STR_LEN-1, "%s:%s", model, inst);
 	if (usemodel)
           Cell(instname, model, ctop, cbot);
 	else
@@ -1121,19 +1121,19 @@ skip_ends:
 	 SpiceSkipNewLine();
      }
      else {
-        char rtop[100], rbot[100];
-	rtop[99] = '\0';
-	rbot[99] = '\0';
+        char rtop[MAX_STR_LEN], rbot[MAX_STR_LEN];
+	rtop[MAX_STR_LEN-1] = '\0';
+	rbot[MAX_STR_LEN-1] = '\0';

        if (!(*CellStackPtr)) {
 	  CellDef(fname, filenum);
 	  PushStack(fname, CellStackPtr);
        }
-        strncpy(inst, nexttok + 1, 99); SpiceTokNoNewline(); 
+        strncpy(inst, nexttok + 1, MAX_STR_LEN-1); SpiceTokNoNewline(); 
        if (nexttok == NULL) goto baddevice;
-        strncpy(rtop, nexttok, 99);  SpiceTokNoNewline();
+        strncpy(rtop, nexttok, MAX_STR_LEN-1);  SpiceTokNoNewline();
        if (nexttok == NULL) goto baddevice;
-        strncpy(rbot, nexttok, 99);   SpiceTokNoNewline();
+        strncpy(rbot, nexttok, MAX_STR_LEN-1);   SpiceTokNoNewline();
        /* make sure all the nodes exist */
        if (LookupObject(rtop, CurrentCell) == NULL) Node(rtop);
        if (LookupObject(rbot, CurrentCell) == NULL) Node(rbot);
@@ -1152,7 +1152,7 @@ skip_ends:

 	model[0] = '\0';
 	if ((nexttok != NULL) && ((eqptr = strchr(nexttok, '=')) == NULL))
-	   snprintf(model, 99, "%s", nexttok);
+	   snprintf(model, MAX_STR_LEN-1, "%s", nexttok);

 	/* Any other device properties? */
        while (nexttok != NULL) {
@@ -1164,7 +1164,7 @@ skip_ends:
 	   }
 	   else if (!strncmp(nexttok, "$[", 2)) {
 	      // Support for CDL modeled resistor format
-	      snprintf(model, 99, "%s", nexttok + 2);
+	      snprintf(model, MAX_STR_LEN-1, "%s", nexttok + 2);
 	      if ((eqptr = strchr(model, ']')) != NULL)
 		 *eqptr = '\0';
 	   }
@@ -1197,7 +1197,7 @@ skip_ends:
 	else
 	   strcpy(model, "r");		/* Use default resistor model */

-	snprintf(instname, 255, "%s:%s", model, inst);
+	snprintf(instname, MAX_STR_LEN-1, "%s:%s", model, inst);
 	if (usemodel)
 	   Cell(instname, model, rtop, rbot);
 	else
@@ -1208,25 +1208,25 @@ skip_ends:
      }
    }
    else if (toupper(nexttok[0]) == 'D') {	/* diode */
-      char cathode[100], anode[100];
-      cathode[99] = '\0';
-      anode[99] = '\0';
+      char cathode[MAX_STR_LEN], anode[MAX_STR_LEN];
+      cathode[MAX_STR_LEN-1] = '\0';
+      anode[MAX_STR_LEN-1] = '\0';

      if (!(*CellStackPtr)) {
 	CellDef(fname, filenum);
 	PushStack(fname, CellStackPtr);
      }
-      strncpy(inst, nexttok + 1, 99); SpiceTokNoNewline(); 
+      strncpy(inst, nexttok + 1, MAX_STR_LEN-1); SpiceTokNoNewline(); 
      if (nexttok == NULL) goto baddevice;
-      strncpy(anode, nexttok, 99);   SpiceTokNoNewline();
+      strncpy(anode, nexttok, MAX_STR_LEN-1);   SpiceTokNoNewline();
      if (nexttok == NULL) goto baddevice;
-      strncpy(cathode, nexttok, 99); SpiceTokNoNewline();
+      strncpy(cathode, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
      /* make sure all the nodes exist */
      if (LookupObject(anode, CurrentCell) == NULL) Node(anode);
      if (LookupObject(cathode, CurrentCell) == NULL) Node(cathode);

      /* Read the device model */
-      snprintf(model, 99, "%s", nexttok);
+      snprintf(model, MAX_STR_LEN-1, "%s", nexttok);

      while (nexttok != NULL)
      {
@@ -1255,7 +1255,7 @@ skip_ends:
 	 Fprintf(stderr, "Device \"%s\" has wrong number of ports for a diode.\n");
 	 goto baddevice;
      }
-      snprintf(instname, 255, "%s:%s", model, inst);
+      snprintf(instname, MAX_STR_LEN-1, "%s:%s", model, inst);
      Cell(instname, model, anode, cathode);
      pobj = LinkProperties(model, kvlist);
      ReduceExpressions(pobj, NULL, CurrentCell, TRUE);
@@ -1268,25 +1268,25 @@ skip_ends:
 	 SpiceSkipNewLine();
      }
      else {
-        char node1[100], node2[100], node3[100], node4[100];
-	node1[99] = '\0';
-	node2[99] = '\0';
-	node3[99] = '\0';
-	node4[99] = '\0';
+        char node1[MAX_STR_LEN], node2[MAX_STR_LEN], node3[MAX_STR_LEN], node4[MAX_STR_LEN];
+	node1[MAX_STR_LEN-1] = '\0';
+	node2[MAX_STR_LEN-1] = '\0';
+	node3[MAX_STR_LEN-1] = '\0';
+	node4[MAX_STR_LEN-1] = '\0';

        if (!(*CellStackPtr)) {
 	  CellDef(fname, filenum);
 	  PushStack(fname, CellStackPtr);
        }
-        strncpy(inst, nexttok + 1, 99); SpiceTokNoNewline(); 
+        strncpy(inst, nexttok + 1, MAX_STR_LEN-1); SpiceTokNoNewline(); 
        if (nexttok == NULL) goto baddevice;
-        strncpy(node1, nexttok, 99);  SpiceTokNoNewline();
+        strncpy(node1, nexttok, MAX_STR_LEN-1);  SpiceTokNoNewline();
        if (nexttok == NULL) goto baddevice;
-        strncpy(node2, nexttok, 99);   SpiceTokNoNewline();
+        strncpy(node2, nexttok, MAX_STR_LEN-1);   SpiceTokNoNewline();
        if (nexttok == NULL) goto baddevice;
-        strncpy(node3, nexttok, 99);   SpiceTokNoNewline();
+        strncpy(node3, nexttok, MAX_STR_LEN-1);   SpiceTokNoNewline();
        if (nexttok == NULL) goto baddevice;
-        strncpy(node4, nexttok, 99);   SpiceTokNoNewline();
+        strncpy(node4, nexttok, MAX_STR_LEN-1);   SpiceTokNoNewline();
        /* make sure all the nodes exist */
        if (LookupObject(node1, CurrentCell) == NULL) Node(node1);
        if (LookupObject(node2, CurrentCell) == NULL) Node(node2);
@@ -1298,7 +1298,7 @@ skip_ends:

 	model[0] = '\0';
 	if ((nexttok != NULL) && ((eqptr = strchr(nexttok, '=')) == NULL))
-	   snprintf(model, 99, "%s", nexttok);
+	   snprintf(model, MAX_STR_LEN-1, "%s", nexttok);

 	/* Any other device properties? */
        while (nexttok != NULL) {
@@ -1334,7 +1334,7 @@ skip_ends:
 	else
 	   strcpy(model, "t");		/* Use default xline model */

-	snprintf(instname, 255, "%s:%s", model, inst);
+	snprintf(instname, MAX_STR_LEN-1, "%s:%s", model, inst);

 	if (usemodel)
 	   Cell(instname, model, node1, node2, node3, node4);
@@ -1347,20 +1347,20 @@ skip_ends:
      }
    }
    else if (toupper(nexttok[0]) == 'L') {	/* inductor */
-      char end_a[100], end_b[100];
+      char end_a[MAX_STR_LEN], end_b[MAX_STR_LEN];
      int usemodel = 0;
-      end_a[99] = '\0';
-      end_b[99] = '\0';
+      end_a[MAX_STR_LEN-1] = '\0';
+      end_b[MAX_STR_LEN-1] = '\0';

      if (!(*CellStackPtr)) {
 	CellDef(fname, filenum);
 	PushStack(fname, CellStackPtr);
      }
-      strncpy(inst, nexttok + 1, 99); SpiceTokNoNewline(); 
+      strncpy(inst, nexttok + 1, MAX_STR_LEN-1); SpiceTokNoNewline(); 
      if (nexttok == NULL) goto baddevice;
-      strncpy(end_a, nexttok, 99);   SpiceTokNoNewline();
+      strncpy(end_a, nexttok, MAX_STR_LEN-1);   SpiceTokNoNewline();
      if (nexttok == NULL) goto baddevice;
-      strncpy(end_b, nexttok, 99); SpiceTokNoNewline();
+      strncpy(end_b, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
      /* make sure all the nodes exist */
      if (LookupObject(end_a, CurrentCell) == NULL) Node(end_a);
      if (LookupObject(end_b, CurrentCell) == NULL) Node(end_b);
@@ -1379,7 +1379,7 @@ skip_ends:

      model[0] = '\0';
      if ((nexttok != NULL) && ((eqptr = strchr(nexttok, '=')) == NULL))
-	  snprintf(model, 99, "%s", nexttok);
+	  snprintf(model, MAX_STR_LEN-1, "%s", nexttok);

      /* Any other device properties? */
      while (nexttok != NULL)
@@ -1417,7 +1417,7 @@ skip_ends:
      else
 	 strcpy(model, "l");		/* Use default inductor model */

-      snprintf(instname, 255, "%s:%s", model, inst);
+      snprintf(instname, MAX_STR_LEN-1, "%s:%s", model, inst);
      if (usemodel)
 	 Cell(instname, model, end_a, end_b);
      else
@@ -1431,25 +1431,38 @@ skip_ends:
    /* black-box subcircuits (class MODULE):  V, I, E	*/

    else if (toupper(nexttok[0]) == 'V') {	/* voltage source */
-      char pos[100], neg[100];
-      pos[99] = '\0';
-      neg[99] = '\0';
+      char pos[MAX_STR_LEN], neg[MAX_STR_LEN];
+      pos[MAX_STR_LEN-1] = '\0';
+      neg[MAX_STR_LEN-1] = '\0';

      if (!(*CellStackPtr)) {
 	CellDef(fname, filenum);
 	PushStack(fname, CellStackPtr);
      }
-      strncpy(inst, nexttok + 1, 99); SpiceTokNoNewline(); 
+      strncpy(inst, nexttok + 1, MAX_STR_LEN-1); SpiceTokNoNewline(); 
      if (nexttok == NULL) goto baddevice;
-      strncpy(pos, nexttok, 99);   SpiceTokNoNewline();
+      strncpy(pos, nexttok, MAX_STR_LEN-1);   SpiceTokNoNewline();
      if (nexttok == NULL) goto baddevice;
-      strncpy(neg, nexttok, 99); SpiceTokNoNewline();
+      strncpy(neg, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
      if (nexttok == NULL) goto baddevice;
      /* make sure all the nodes exist */
      if (LookupObject(pos, CurrentCell) == NULL) Node(pos);
      if (LookupObject(neg, CurrentCell) == NULL) Node(neg);

-      /* Any device properties? */
+      /* Get voltage value (if present); save as property "value" */
+
+      if (nexttok != NULL) {
+	 if (matchnocase(nexttok, "DC")) {
+	     SpiceTokNoNewline();
+	 }
+      }
+      if (nexttok != NULL) {
+	 if (StringIsValueOrExpression(nexttok)) {
+	     AddProperty(&kvlist, "value", nexttok);
+	 }
+      }
+
+      /* Any other device properties? */
      while (nexttok != NULL)
      {
 	 SpiceTokNoNewline();
@@ -1477,7 +1490,7 @@ skip_ends:
      else if (CountPorts(model, filenum) != 2) {
 	 /* Modeled device:  Make sure it has the right number of ports */
 	 Fprintf(stderr, "Device \"%s\" has wrong number of ports for a "
-			"voltage source.\n");
+			"voltage source.\n", inst);
 	 goto baddevice;
      }
      Cell(instname, model, pos, neg);
@@ -1486,19 +1499,19 @@ skip_ends:
      DeleteProperties(&kvlist);
    }
    else if (toupper(nexttok[0]) == 'I') {	/* current source */
-      char pos[100], neg[100];
-      pos[99] = '\0';
-      neg[99] = '\0';
+      char pos[MAX_STR_LEN], neg[MAX_STR_LEN];
+      pos[MAX_STR_LEN-1] = '\0';
+      neg[MAX_STR_LEN-1] = '\0';

      if (!(*CellStackPtr)) {
 	CellDef(fname, filenum);
 	PushStack(fname, CellStackPtr);
      }
-      strncpy(inst, nexttok + 1, 99); SpiceTokNoNewline(); 
+      strncpy(inst, nexttok + 1, MAX_STR_LEN-1); SpiceTokNoNewline(); 
      if (nexttok == NULL) goto baddevice;
-      strncpy(pos, nexttok, 99);   SpiceTokNoNewline();
+      strncpy(pos, nexttok, MAX_STR_LEN-1);   SpiceTokNoNewline();
      if (nexttok == NULL) goto baddevice;
-      strncpy(neg, nexttok, 99); SpiceTokNoNewline();
+      strncpy(neg, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
      /* make sure all the nodes exist */
      if (LookupObject(pos, CurrentCell) == NULL) Node(pos);
      if (LookupObject(neg, CurrentCell) == NULL) Node(neg);
@@ -1540,25 +1553,25 @@ skip_ends:
      DeleteProperties(&kvlist);
    }
    else if (toupper(nexttok[0]) == 'E') {	/* controlled voltage source */
-      char pos[100], neg[100], ctrlp[100], ctrln[100];
-      pos[99] = '\0';
-      neg[99] = '\0';
-      ctrlp[99] = '\0';
-      ctrln[99] = '\0';
+      char pos[MAX_STR_LEN], neg[MAX_STR_LEN], ctrlp[MAX_STR_LEN], ctrln[MAX_STR_LEN];
+      pos[MAX_STR_LEN-1] = '\0';
+      neg[MAX_STR_LEN-1] = '\0';
+      ctrlp[MAX_STR_LEN-1] = '\0';
+      ctrln[MAX_STR_LEN-1] = '\0';

      if (!(*CellStackPtr)) {
 	CellDef(fname, filenum);
 	PushStack(fname, CellStackPtr);
      }
-      strncpy(inst, nexttok + 1, 99); SpiceTokNoNewline(); 
+      strncpy(inst, nexttok + 1, MAX_STR_LEN-1); SpiceTokNoNewline(); 
      if (nexttok == NULL) goto baddevice;
-      strncpy(pos, nexttok, 99);   SpiceTokNoNewline();
+      strncpy(pos, nexttok, MAX_STR_LEN-1);   SpiceTokNoNewline();
      if (nexttok == NULL) goto baddevice;
-      strncpy(neg, nexttok, 99); SpiceTokNoNewline();
+      strncpy(neg, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
      if (nexttok == NULL) goto baddevice;
-      strncpy(ctrlp, nexttok, 99); SpiceTokNoNewline();
+      strncpy(ctrlp, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();
      if (nexttok == NULL) goto baddevice;
-      strncpy(ctrln, nexttok, 99); SpiceTokNoNewline();
+      strncpy(ctrln, nexttok, MAX_STR_LEN-1); SpiceTokNoNewline();

      /* make sure all the nodes exist */
      if (LookupObject(pos, CurrentCell) == NULL) Node(pos);
@@ -1606,11 +1619,11 @@ skip_ends:
    }

    else if (toupper(nexttok[0]) == 'X') {	/* subcircuit instances */
-      char instancename[100], subcktname[100];
+      char instancename[MAX_STR_LEN], subcktname[MAX_STR_LEN];
      int itype, in_props;

-      instancename[99] = '\0';
-      subcktname[99] = '\0';
+      instancename[MAX_STR_LEN-1] = '\0';
+      subcktname[MAX_STR_LEN-1] = '\0';

      struct portelement {
 	char *name;
@@ -1620,8 +1633,8 @@ skip_ends:
      struct portelement *head, *tail, *scan, *scannext;
      struct objlist *obptr;

-      snprintf(instancename, 99, "%s", nexttok + 1);
-      strncpy(instancename, nexttok + 1, 99);
+      snprintf(instancename, MAX_STR_LEN-1, "%s", nexttok + 1);
+      strncpy(instancename, nexttok + 1, MAX_STR_LEN-1);
      if (!(*CellStackPtr)) {
 	CellDef(fname, filenum);
 	PushStack(fname, CellStackPtr);
@@ -1729,14 +1742,14 @@ skip_ends:
      /* names.								  */

      if (strncmp(instancename, scan->name, strlen(scan->name))) {
-         snprintf(subcktname, 99, "%s:%s", scan->name, instancename);
+         snprintf(subcktname, MAX_STR_LEN-1, "%s:%s", scan->name, instancename);
         strcpy(instancename, subcktname);
      }
      else {
-         snprintf(subcktname, 99, "/%s", instancename);
+         snprintf(subcktname, MAX_STR_LEN-1, "/%s", instancename);
         strcpy(instancename, subcktname);
      }
-      snprintf(subcktname, 99, "%s", scan->name);
+      snprintf(subcktname, MAX_STR_LEN-1, "%s", scan->name);

      if (scan == head) {
 	 head = NULL;
@@ -1770,6 +1783,18 @@ skip_ends:
 	 ReopenCellDef((*CellStackPtr)->cellname, filenum);		/* Reopen */
 	 update = 1;
      }
+      else if (tp->flags & CELL_VERILOG) {
+	 if (tp->flags & CELL_PLACEHOLDER) {
+	    /* Flag this as an error.  To do:  Rearrange the verilog instance pins to	*/
+	    /* match the SPICE subcircuit pin order.					*/
+	    Fprintf(stderr, "Error:  SPICE subcircuit %s should be read before verilog "
+			"module using it, or pins may not match!\n", subcktname);
+	 }
+	 else {
+	    Fprintf(stderr, "Error:  SPICE subcircuit %s redefines a verilog module!\n",
+			subcktname);
+	 }
+      }

      /* nexttok is now NULL, scan->name points to class */

@@ -1972,7 +1997,7 @@ void IncludeSpice(char *fname, int parent, struct cellstack **CellStackPtr,
 		int blackbox)
 {
  int filenum = -1;
-  char name[256];
+  char name[MAX_STR_LEN];

  /* If fname does not begin with "/", then assume that it is	*/
  /* in the same relative path as its parent.			*/
@@ -803,6 +803,56 @@ extern void IncludeVerilog(char *, int, struct cellstack **, int);
 extern void PushStack(char *cellname, struct cellstack **top);
 extern void PopStack(struct cellstack **top);

+/*------------------------------------------------------*/
+/* Callback routine for FindInstanceOf()		*/
+/* NOTE:  This casts a (struct objlist) pointer to a	*/
+/* (struct nlist) pointer for the purpose of using	*/
+/* RecurseCellHashTable2().  FindInstanceOf() casts it	*/
+/* back into a (struct objlist) pointer.		*/
+/*------------------------------------------------------*/
+
+struct nlist *findInstance(struct hashlist *p, void *clientdata)
+{
+    struct nlist *ptr;
+    struct objlist *ob;
+    struct nlist *tref = (struct nlist *)clientdata;
+
+    ptr = (struct nlist *)(p->ptr);
+    if (ptr->file != tref->file) return NULL;
+
+    ob = LookupInstance(tref->name, ptr);
+    return (struct nlist *)ob;
+}
+
+/*------------------------------------------------------*/
+/* Routine to find the first instance of a cell		*/
+/*------------------------------------------------------*/
+
+struct objlist *FindInstanceOf(struct nlist *tc)
+{
+    return (struct objlist *)RecurseCellHashTable2(findInstance, (void *)tc);
+}
+
+/*------------------------------------------------------*/
+/* Given a reference cell pointer tref and a port name	*/
+/* portname, check if portname is a port of tref.  If	*/
+/* not, then call Port() to add one.  If tref is NULL,	*/
+/* then always add the port.				*/
+/*------------------------------------------------------*/
+
+void CheckPort(struct objlist *tref, char *portname)
+{
+    struct objlist *ob;
+
+    if (tref != NULL) {
+	for (ob = CurrentCell->cell; ob && (ob->type == PORT); ob = ob->next) {
+	    if ((*matchfunc)(ob->name, portname))
+		return;
+	}
+    }
+    Port(portname);
+}
+
 /*------------------------------------------------------*/
 /* Read a verilog structural netlist			*/
 /*------------------------------------------------------*/
@@ -816,13 +866,13 @@ void ReadVerilogFile(char *fname, int filenum, struct cellstack **CellStackPtr,
  char devtype, in_module, in_param;
  char *eqptr, *matchptr;
  struct keyvalue *kvlist = NULL;
-  char inst[256], model[256], instname[256], portname[256], pkey[256];
+  char inst[MAX_STR_LEN], model[MAX_STR_LEN], instname[MAX_STR_LEN], portname[MAX_STR_LEN], pkey[MAX_STR_LEN];
  struct nlist *tp;
-  struct objlist *parent, *sobj, *nobj, *lobj, *pobj;
+  struct objlist *parent, *sobj, *nobj, *lobj, *pobj, *cref;

-  inst[255] = '\0';
-  model[255] = '\0';
-  instname[255] = '\0';
+  inst[MAX_STR_LEN-1] = '\0';
+  model[MAX_STR_LEN-1] = '\0';
+  instname[MAX_STR_LEN-1] = '\0';
  in_module = (char)0;
  in_param = (char)0;

@@ -938,6 +988,7 @@ void ReadVerilogFile(char *fname, int filenum, struct cellstack **CellStackPtr,
          InputParseError(stderr);
      }
      in_module = (char)1;
+      cref = NULL;

      /* Save pointer to current cell */
      if (CurrentCell != NULL)
@@ -947,8 +998,9 @@ void ReadVerilogFile(char *fname, int filenum, struct cellstack **CellStackPtr,

      /* Check for existence of the cell.  We may need to rename it. */

-      snprintf(model, 99, "%s", nexttok);
+      snprintf(model, MAX_STR_LEN-1, "%s", nexttok);
      tp = LookupCellFile(nexttok, filenum);
+      hasports = (char)0;

      /* Check for name conflict with duplicate cell names	*/
      /* This may mean that the cell was used before it was	*/
@@ -986,23 +1038,48 @@ void ReadVerilogFile(char *fname, int filenum, struct cellstack **CellStackPtr,
         CellDef(nexttok, filenum);
         tp = LookupCellFile(nexttok, filenum);
      }
-      else if (tp != NULL) {	/* Make a new definition for an empty cell */
-	 FreePorts(nexttok);
-	 CellDelete(nexttok, filenum);	/* This removes any PLACEHOLDER flag */
+      else if (tp != NULL) {	/* Cell exists, but as a placeholder */
+	 struct nlist *tptmp = NULL;
+	 char ctemp[8];
+	 int n = 0;
+
+	 /* This redefines a placeholder module to an unused temporary cell name */
+         while (1) {
+	    sprintf(ctemp, "%d", n);
+            tptmp = LookupCellFile(ctemp, filenum);
+	    if (tptmp == NULL) break;
+	    n++;
+	 }
+	 CellRehash(nexttok, ctemp, filenum);
+	 tptmp = LookupCellFile(ctemp, filenum);
+
+	 /* Create a new module definition */
 	 CellDef(model, filenum);
 	 tp = LookupCellFile(model, filenum);
+
+	 /* Find an instance of this module in the netlist */
+	 cref = FindInstanceOf(tp);
+	 if ((cref != NULL) && (cref->name != NULL)) {
+	    hasports = (char)1;
+	    /* Copy ports from the original parent cell to the new parent cell */
+	    for (pobj = tptmp->cell; pobj && (pobj->type == PORT); pobj = pobj->next)
+		Port(pobj->name);
+	 }
+	 /* Remove the original cell definition */
+	 FreePorts(ctemp);
+	 CellDelete(ctemp, filenum);	/* This removes any PLACEHOLDER flag */
      }
      else if (tp == NULL) {	/* Completely new cell, no name conflict */
         CellDef(model, filenum);
         tp = LookupCellFile(model, filenum);
      }

-      hasports = (char)0;
      inlined_decls = (char)0;

      if (tp != NULL) {
 	 struct bus wb, *nb;

+	 tp->flags |= CELL_VERILOG;
 	 PushStack(tp->name, CellStackPtr);

 	 /* Need to support both types of I/O lists:  Those	*/
@@ -1071,7 +1148,7 @@ void ReadVerilogFile(char *fname, int filenum, struct cellstack **CellStackPtr,
 			   if (GetBusTok(&wb) != 0) {
 			      // Didn't parse as a bus, so wing it
 			      wb.start = wb.end = -1;
-			      Port(nexttok);
+			      CheckPort(cref, nexttok);
 			   }
 			}
 			else {
@@ -1079,13 +1156,13 @@ void ReadVerilogFile(char *fname, int filenum, struct cellstack **CellStackPtr,
 			      if (wb.start > wb.end) {
 				 for (i = wb.start; i >= wb.end; i--) {
 				    sprintf(portname, "%s[%d]", nexttok, i);
-				    Port(portname);
+				    CheckPort(cref, portname);
 				 }
 			      }
 			      else {
 				 for (i = wb.start; i <= wb.end; i++) {
 				    sprintf(portname, "%s[%d]", nexttok, i);
-				    Port(portname);
+				    CheckPort(cref, portname);
 				 }
 			      }
 			      /* Also register this port as a bus */
@@ -1097,7 +1174,7 @@ void ReadVerilogFile(char *fname, int filenum, struct cellstack **CellStackPtr,
 			      wb.start = wb.end = -1;
 			   }
 			   else {
-			      Port(nexttok);
+			      CheckPort(cref, nexttok);
 			   }
 			}
 		        hasports = 1;
@@ -1153,7 +1230,7 @@ skip_endmodule:
 		if (GetBusTok(&wb) != 0) {
 		    // Didn't parse as a bus, so wing it
 		    wb.start = wb.end = -1;
-		    Port(nexttok);
+		    CheckPort(cref, nexttok);
 		}
 	    }
 	    else if (!match(nexttok, ",")) {
@@ -1161,13 +1238,13 @@ skip_endmodule:
 		    if (wb.start > wb.end) {
 			for (i = wb.start; i >= wb.end; i--) {
 			    sprintf(portname, "%s[%d]", nexttok, i);
-			    Port(portname);
+			    CheckPort(cref, portname);
 			}
 		    }
 		    else {
 			for (i = wb.start; i <= wb.end; i++) {
 			    sprintf(portname, "%s[%d]", nexttok, i);
-			    Port(portname);
+			    CheckPort(cref, portname);
 			}
 		    }
 		    /* Also register this port as a bus */
@@ -1178,7 +1255,7 @@ skip_endmodule:
 		    wb.start = wb.end = -1;
 		}
 		else {
-		    Port(nexttok);
+		    CheckPort(cref, nexttok);
 		}
 	    }
 	    hasports = 1;
@@ -1194,6 +1271,7 @@ skip_endmodule:
          InputParseError(stderr);
      }
      in_module = (char)0;
+      cref = NULL;

      if (*CellStackPtr) PopStack(CellStackPtr);
      if (*CellStackPtr) ReopenCellDef((*CellStackPtr)->cellname, filenum);
@@ -1340,7 +1418,7 @@ skip_endmodule:
    }
    else if (match(nexttok, "wire") || match(nexttok, "assign")) {	/* wire = node */
 	struct bus wb, wb2, *nb;
-	char nodename[128], noderoot[100];
+	char nodename[MAX_STR_LEN], noderoot[MAX_STR_LEN];
 	int is_wire = match(nexttok, "wire");
 	int j;
 	struct objlist *lhs, *rhs;
@@ -1438,7 +1516,7 @@ skip_endmodule:
 	//    "assign" using any boolean arithmetic is not structural verilog.

 	if (nexttok && match(nexttok, "=")) {
-	    char assignname[128], assignroot[100];
+	    char assignname[MAX_STR_LEN], assignroot[MAX_STR_LEN];

 	    i = wb.start;
 	    while (1) {
@@ -1552,12 +1630,12 @@ skip_endmodule:
      goto skip_endmodule;
    }
    else {	/* module instances */
-      char instancename[100], modulename[100];
+      char instancename[MAX_STR_LEN], modulename[MAX_STR_LEN];
      int itype, arraystart, arrayend, arraymax, arraymin;
      char ignore;

-      instancename[99] = '\0';
-      modulename[99] = '\0';
+      instancename[MAX_STR_LEN-1] = '\0';
+      modulename[MAX_STR_LEN-1] = '\0';

      struct portelement {
 	char *name;	// Name of port in subcell
@@ -1570,7 +1648,7 @@ skip_endmodule:
      struct portelement *head, *tail, *scan, *last, *scannext;
      struct objlist *obptr;

-      strncpy(modulename, nexttok, 99);
+      strncpy(modulename, nexttok, MAX_STR_LEN-1);

      /* If module name is a verilog primitive, then treat the module as a  */
      /* black box (this is not a complete list.  Preferable to use hash    */
@@ -1648,7 +1726,7 @@ nextinst:
 	 }
      }

-      strncpy(instancename, nexttok, 99);
+      strncpy(instancename, nexttok, MAX_STR_LEN-1);
      /* Printf("Diagnostic:  new instance is %s\n", instancename); */
      SkipTokComments(VLOG_DELIMITERS);

@@ -1669,7 +1747,7 @@ nextinst:

 	 // Read the pin list
         while (nexttok != NULL) {
-	    SkipTokComments(VLOG_DELIMITERS);
+	    SkipTokComments(VLOG_PIN_CHECK_DELIMITERS);
 	    if (match(nexttok, ")")) break;
 	    else if (match(nexttok, ",")) continue;

@@ -1698,7 +1776,7 @@ nextinst:
 	       }
 	       SkipTokComments(VLOG_PIN_CHECK_DELIMITERS);
 	       if (match(nexttok, ")")) {
-		  char localnet[100];
+		  char localnet[MAX_STR_LEN];
 		  // Empty parens, so create a new local node
 		  savetok = (char)1;
 		  if (arraystart != -1) {
@@ -1830,7 +1908,7 @@ nextinst:
      tp = LookupCellFile(modulename, filenum);
      if (tp == NULL) {
         struct bus wb, pb;
-	 char defport[128];
+	 char defport[MAX_STR_LEN];

 	 Fprintf(stdout, "Creating placeholder cell definition for "
 			"module %s.\n", modulename);
@@ -1921,7 +1999,7 @@ nextinst:
 	 if (portstart != -1) {
 	    struct bus wb;
 	    struct portelement *new_port;
-	    char vname[256];
+	    char vname[MAX_STR_LEN];
 	    int j, result;
 	    struct objlist *bobj;
 	    char *bptr;
@@ -2074,7 +2152,7 @@ nextinst:
      for (i = arraymin; i <= arraymax; i++) {
 	 char *brackptr;
 	 int j;
-	 char locinst[128];
+	 char locinst[MAX_STR_LEN];

         if (i != -1)
 	    sprintf(locinst, "%s[%d]", instancename, i);
@@ -2109,13 +2187,13 @@ nextinst:
 		  scan = scan->next;
 	       }
 	       if (scan == NULL) {
-		  char localnet[100];
+		  char localnet[MAX_STR_LEN];

 		  /* Assume an implicit unconnected pin */
 		  sprintf(localnet, "_noconnect_%d_", localcount++);
 		  Node(localnet);
 		  join(localnet, obptr->name);
-		  Fprintf(stderr,
+		  Fprintf(stdout,
 			 "Note:  Implicit pin %s in instance %s of %s in cell %s\n",
 			 obpinname, locinst, modulename, CurrentCell->name);
 	       }
@@ -2129,7 +2207,7 @@ nextinst:
 		   if (arraystart == -1) {
 		       // Port may be an array
 		       int range;
-		       char pinname[128];
+		       char pinname[MAX_STR_LEN];

 		       // Check if port is an array
 		       if (obpinidx == -1) {
@@ -2154,7 +2232,7 @@ nextinst:
 		   }
 		   else {
 		       // Instance must be an array
-		       char netname[128];
+		       char netname[MAX_STR_LEN];
 		       int slice, portlen, siglen;

 		       /* Get the array size of the port for bit slicing */
@@ -2204,11 +2282,11 @@ nextinst:
 	          for (scan = head; scan; scan = scan->next) {
 	             if (!(scan->flags & PORT_FOUND)) {
 		        if (tp->flags & CELL_PLACEHOLDER) {
-			   char tempname[128];
+			   char tempname[MAX_STR_LEN];
 			   int maxnode;

-		           /* This pin was probably implicit in the first call */
-		           /* and so it needs to be added to the definition.	 */
+		           /* This pin was probably implicit in the first call	*/
+		           /* and so it needs to be added to the definition.	*/

 			   ReopenCellDef(modulename, filenum);
 		           Port(scan->name);
@@ -2228,6 +2306,9 @@ nextinst:
 			   obptr->next = nobj;
      			   HashPtrInstall(nobj->name, nobj, &(CurrentCell->objdict));

+			   /* Ensure that CurrentTail is correct */
+			   if (obptr == CurrentTail) CurrentTail = nobj;
+
 	           	   if (LookupObject(scan->net, CurrentCell) == NULL)
 			      Node(scan->net);
 	           	   join(scan->net, nobj->name);
@@ -2262,13 +2343,14 @@ nextinst:
 		  	   	    sprintf(tempname, "_noconnect_%d_", localcount++);
 		  	   	    Node(tempname);
 		  	   	    join(tempname, nobj->name);
-		  	   	    Fprintf(stderr, "Note:  Implicit pin %s in instance "
+		  	   	    Fprintf(stdout, "Note:  Implicit pin %s in instance "
 						"%s of %s in cell %s\n",
 			 			scan->name, sobj->instance.name,
 						modulename, CurrentCell->name);
 				 }
 			      }
 			   }
+			   obptr = obptr->next;
 		        }
 		        else {
 		           Fprintf(stderr, "Error:  Instance %s has pin %s which is "
@@ -2428,7 +2510,7 @@ void IncludeVerilog(char *fname, int parent, struct cellstack **CellStackPtr,
 		int blackbox)
 {
  int filenum = -1;
-  char name[256];
+  char name[MAX_STR_LEN];

  /* If fname does not begin with "/", then assume that it is	*/
  /* in the same relative path as its parent.			*/
@@ -65,10 +65,10 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */

 Widget toplevel = NULL;

-char GlobalFileName[100], 
-  GlobalCellName[100], 
-  GlobalOtherName[100],
-  GlobalDataName[100];
+char GlobalFileName[MAX_STR_LEN], 
+  GlobalCellName[MAX_STR_LEN], 
+  GlobalOtherName[MAX_STR_LEN],
+  GlobalDataName[MAX_STR_LEN];

 /*********************************************************
 * Menu structure:  attaches label string to a function,
@@ -1708,7 +1708,7 @@ void X_main_loop(int argc, char *argv[])

 XmStringCharSet cs = "ISOLatin1";

-static char prompt_response[100];
+static char prompt_response[MAX_STR_LEN];
 int prompt_done;
 int calling_editor;  /* which string are we trying to get ? */
 #define FILE_NAME 1
@@ -33,7 +33,7 @@ void STRCPY(char *dest, char *source)

 int main(int argc, char *argv[])
 {
-  char cell1[200], cell2[200];
+  char cell1[MAX_STR_LEN], cell2[MAX_STR_LEN];

  Debug = 0;
  if (argc != 1) {
@@ -51,7 +51,7 @@ void STRCPY(char *dest, char *source)
 int main(int argc, char *argv[])
 {
 #ifndef HAVE_GETOPT
-  char cell1[200], cell2[200];
+  char cell1[MAX_STR_LEN], cell2[MAX_STR_LEN];
  int filenum = -1;

  Debug = 0;
@@ -67,7 +67,7 @@ int main(int argc, char *argv[])
  STRCPY(cell2, ReadNetlist(argv[2], &filenum));
  if (argc == 5) STRCPY(cell2, argv[4]);  /* if explicit cell name specified */
 #else
-  char cell1[200], cell2[200];
+  char cell1[MAX_STR_LEN], cell2[MAX_STR_LEN];
  int usage = 0;
  int args;
  int c;
@@ -47,7 +47,7 @@ void STRCPY(char *dest, char *source)

 int main(int argc, char *argv[])
 {
-  char cellname[200];
+  char cellname[MAX_STR_LEN];
  int filenum = -1;

  Debug = 0;
@@ -62,16 +62,18 @@ proc netgen::convert_to_json {filename lvs_final} {
 	          puts $fjson "      \["
 		  set cktval [lindex $value 0]
 		  foreach pin [lrange $cktval 0 end-1] {
-		     puts $fjson "        \"$pin\","
+		     set pinstr [string map {"\\" "\\\\"} $pin]
+		     puts $fjson "        \"$pinstr\","
 		  }
-		  set pin [lindex $cktval end]
+		  set pin [string map {"\\" "\\\\"} [lindex $cktval end]]
 		  puts $fjson "        \"$pin\""
 	          puts $fjson "      \], \["
 		  set cktval [lindex $value 1]
 		  foreach pin [lrange $cktval 0 end-1] {
-		     puts $fjson "        \"$pin\","
+		     set pinstr [string map {"\\" "\\\\"} $pin]
+		     puts $fjson "        \"$pinstr\","
 		  }
-		  set pin [lindex $cktval end]
+		  set pin [string map {"\\" "\\\\"} [lindex $cktval end]]
 		  puts $fjson "        \"$pin\""
 	          puts $fjson "      \]"
 		  if {$kidx == $nkeys} {
@@ -393,7 +395,7 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
 	 # If argument is a filename then read the list of cells from it;
 	 # otherwise, argument is the list of files itself in quotes or
 	 # braces.
-	 if {![catch {file exists $value}]} {
+	 if {[file exists $value]} {
 	    if {![catch {open $value r} fnf]} {
 	       while {[gets $fnf line] >= 0} {
 		  if {[lindex $line 0] != "#"} {
@@ -532,14 +534,24 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
   }
   set properr {}
   set matcherr {}
-   set pinsgood -1
+   set childMismatch 0		;# 1 indicates black-box child subcircuit mismatch
   while {$endval != {}} {
      if {$dolist == 1} {
         netgen::run -list converge
      } else {
         netgen::run converge
      }
-      netgen::log echo on
+      set pinMismatch 0		;# indicates pin mismatch in top cell
+      set doCheckFlatten 0
+      set doFlatten 0
+      if {[netgen::print queue] == {}} {
+	 set doEquatePins 1 	;# run equate pins on top cell
+      } else {
+	 set doEquatePins 0	;# don't run equate pins unless unique match
+      }
+      set forceMatch 0		;# for pin matching
+      netgen::log echo off
+
      if {[verify equivalent]} {
 	 # Resolve automorphisms by pin and property
 	 if {$dolist == 1} {
@@ -548,96 +560,105 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
            netgen::run resolve
 	 }
 	 set uresult [verify unique]
+	 # uresult:  -3 : unique with property error
+	 #	     -2 : equivalent with port errors
+	 #	     -1 : black box
+	 #	      0 : equivalent but not unique
+	 #	      1 : unique
         if {$uresult == 0} {
+	    netgen::log echo on
 	    netgen::log put "   Networks match locally but not globally.\n"
 	    netgen::log put "   Probably connections are swapped.\n"
 	    netgen::log put "   Check the end of logfile ${logfile} for implicated nodes.\n"
+	    netgen::log echo off
 	    if {$dolist == 1} {
 	       verify -list nodes
 	    } else {
 	       verify nodes
 	    }
-
-	    # Flatten the non-matching subcircuit (but not the top-level cells)
-            if {[netgen::print queue] != {}} {
-	       if {([lsearch $noflat [lindex $endval 0]] == -1) &&
-			([lsearch $noflat [lindex $endval 1]] == -1)} {
-	           netgen::log put "  Flattening non-matched subcircuits $endval\n"
-	           netgen::flatten class "[lindex $endval 0] $fnum1"
-	           netgen::flatten class "[lindex $endval 1] $fnum2"
-	       } else {
-	           netgen::log put "  Continuing with black-boxed subcircuits $endval\n"
-		   lappend matcherr [lindex $endval 0]"($fnum1)"
-		   lappend matcherr [lindex $endval 1]"($fnum2)"
-	           # Match pins
-                   netgen::log echo off
-	           if {$dolist == 1} {
-		       set result [equate -list -force pins "$fnum1 [lindex $endval 0]" \
-				"$fnum2 [lindex $endval 1]"]
-	           } else {
-		       set result [equate -force pins "$fnum1 [lindex $endval 0]" \
-				"$fnum2 [lindex $endval 1]"]
-	           }
-	           if {$result != 0} {
-		       equate classes "$fnum1 [lindex $endval 0]" \
-			        "$fnum2 [lindex $endval 1]"
-	           }
-	           set pinsgood $result
-                   netgen::log echo on
-	       }
-	    }
+	    set doCheckFlatten 1
 	 } else {
-            netgen::log echo off
-	    if {$dolist == 1} {
-		set result [equate -list pins "$fnum1 [lindex $endval 0]" \
-				"$fnum2 [lindex $endval 1]"]
-	    } else {
-		set result [equate pins "$fnum1 [lindex $endval 0]" \
-				"$fnum2 [lindex $endval 1]"]
-	    }
-	    if {$result != 0} {
-		equate classes "$fnum1 [lindex $endval 0]" \
-			 "$fnum2 [lindex $endval 1]"
-	    }
-	    # If $uresult == -1 then these are black-box entries and
-	    # $pinsgood should not be set to the resulting value.
-	    if {$uresult > 0} {
-	        set pinsgood $result
-	    }
-            netgen::log echo on
+	    # Equate pins for black boxes, unique matches (possibly with property
+	    # errors), and unique with port errors
+	    set doEquatePins 1
+	 }
+	 if {$uresult == -1} {		;# black box
+	    set forceMatch 1
+	 } elseif {$uresult == -3} {	;# property error
+	    lappend properr [lindex $endval 0]
+	 } elseif {$uresult == -2} {	;# unmatched pins
+	    set doCheckFlatten 1
 	 }
-	 if {$uresult == 2} {lappend properr [lindex $endval 0]}
      } else {
-	 # Flatten the non-matching subcircuit (but not the top-level cells)
-         if {[netgen::print queue] != {}} {
+	 # not equivalent
+	 netgen::log echo on
+	 # netgen::log put "  DEBUG: not equivalent $endval\n"
+	 netgen::log echo off
+	 set doCheckFlatten 1
+      }
+      if {$doCheckFlatten} {
+	 # Flatten the non-matching subcircuit (but not the top-level cell,
+	 # or cells explicitly prohibited from flattening)
+	 if {[netgen::print queue] != {}} {
 	    if {([lsearch $noflat [lindex $endval 0]] == -1) &&
-		    ([lsearch $noflat [lindex $endval 1]] == -1)} {
-	       netgen::log put "  Flattening non-matched subcircuits $endval\n"
-	       netgen::flatten class "[lindex $endval 0] $fnum1"
-	       netgen::flatten class "[lindex $endval 1] $fnum2"
-	    } else {
+			([lsearch $noflat [lindex $endval 1]] == -1)} {
+	       set doFlatten 1
+	    } else {	
+	       netgen::log echo on
 	       netgen::log put "  Continuing with black-boxed subcircuits $endval\n"
+	       netgen::log echo off
 	       lappend matcherr [lindex $endval 0]"($fnum1)"
-	       lappend matcherr [lindex $endval 0]"($fnum2)"
-	       # Match pins
-               netgen::log echo off
-	       if {$dolist == 1} {
-		   set result [equate -list -force pins "$fnum1 [lindex $endval 0]" \
-			    "$fnum2 [lindex $endval 1]"]
-	       } else {
-		   set result [equate -force pins "$fnum1 [lindex $endval 0]" \
-			    "$fnum2 [lindex $endval 1]"]
-	       }
-	       if {$result != 0} {
-		   equate classes "$fnum1 [lindex $endval 0]" \
-			    "$fnum2 [lindex $endval 1]"
-	       }
-	       set pinsgood $result
-               netgen::log echo on
+	       lappend matcherr [lindex $endval 1]"($fnum2)"
+	       netgen::flatten prohibit "[lindex $endval 0] $fnum1"
+	       netgen::flatten prohibit "[lindex $endval 1] $fnum2"
+	       set doEquatePins 1
+	       set childMismatch 1
+	       set forceMatch 1
 	    }
 	 }
      }
-      netgen::log echo off
+      if {$doEquatePins} {
+	 # Match pins
+	 if {$dolist == 1} {
+	    if {$forceMatch} {
+	       set result [equate -list -force pins "$fnum1 [lindex $endval 0]" \
+				"$fnum2 [lindex $endval 1]"]
+	    } else {
+	       set result [equate -list pins "$fnum1 [lindex $endval 0]" \
+				"$fnum2 [lindex $endval 1]"]
+	    }
+	 } else {
+	    if {$forceMatch} {
+	       set result [equate -force pins "$fnum1 [lindex $endval 0]" \
+				"$fnum2 [lindex $endval 1]"]
+	    } else {
+	       set result [equate pins "$fnum1 [lindex $endval 0]" \
+				"$fnum2 [lindex $endval 1]"]
+	    }
+	 }
+	 if {$result >= 0} {
+	    equate classes "$fnum1 [lindex $endval 0]" \
+		        "$fnum2 [lindex $endval 1]"
+	 }
+	 # Do not set pinMismatch for black boxes
+	 if {$result < 0} {
+	    if {$result == -1 && [netgen::print queue] != {} && $forceMatch != 1} {
+               # flatten pin mismatch, but not empty cells (-2) or top cell or
+	       # cells prohibited from flattening.
+	       set doFlatten 1
+	    }
+	 } elseif {[netgen::print queue] == {} && $result == 0} {
+	    set pinMismatch 1
+	 }
+      }
+      if {$doFlatten} {
+	 netgen::log echo on
+	 netgen::log put "  Flattening non-matched subcircuits $endval\n"
+	 netgen::log echo off
+	 netgen::flatten class "[lindex $endval 0] $fnum1"
+	 netgen::flatten class "[lindex $endval 1] $fnum2"
+      }
+
      if {$dolist == 1} {
         catch {lappend lvs_final $lvs_out}
         set lvs_out {}
@@ -646,20 +667,23 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
         set endval [netgen::compare hierarchical]
      }
   }
-   netgen::log echo off
-   puts stdout "Result: " nonewline
   netgen::log echo on
-   if {$pinsgood == 0} {
-      # NOTE:  Need to disambiguate these two cases. . .
-      netgen::log put "Cells failed matching, or top level cell failed pin matching.\n"
+   netgen::log put "\nFinal result: "
+   if {$pinMismatch || $childMismatch} {
+      if {$childMismatch} {
+	 netgen::log put "Subcell(s) failed matching.\n"
+      }
+      if {$pinMismatch} {
+	 netgen::log put "Top level cell failed pin matching.\n"
+      }
   } else {
      verify only
   }
   if {$properr != {}} {
-      netgen::log put "The following cells had property errors:\n " [regsub -all { } $properr "\n "] "\n"
+      netgen::log put "\nThe following cells had property errors:\n " [regsub -all { } $properr "\n "] "\n"
   }
   if {$matcherr != {}} {
-      netgen::log put "The following subcells failed to match:\n " [regsub -all { } $matcherr "\n "] "\n"
+      netgen::log put "\nThe following subcells failed to match:\n " [regsub -all { } $matcherr "\n "] "\n"
   }
   if {$dolog} {
      netgen::log end
@@ -1056,6 +1056,12 @@ _netgen_flatten(ClientData clientData,
            FlattenInstancesOf(repstr, filenum);
 	 }
      }
+      else if (!strcmp(argv, "prohibit") || !strcmp(argv, "deny")) {
+	 tp = GetTopCell(filenum);
+	 Printf("Will not flatten instances of %s in file %s\n", repstr, tp->name);
+	 /* Mark cell as placeholder so it will not be flattened */
+	 tp->flags |= CELL_PLACEHOLDER;
+      }
      else {
 	 Tcl_WrongNumArgs(interp, 1, objv, "class valid_cellname");
 	 return TCL_ERROR;
@@ -1931,9 +1937,17 @@ _netgen_log(ClientData clientData,
   switch(index) {
      case START_IDX:
 	 LoggingFile = fopen(LogFileName, "w");
+	 if (!LoggingFile) {
+	    Tcl_SetResult(interp, "Could not open log file.", NULL);
+	    return TCL_ERROR;
+	 }
 	 break;
      case RESUME_IDX:
 	 LoggingFile = fopen(LogFileName, "a");
+	 if (!LoggingFile) {
+	    Tcl_SetResult(interp, "Could not open log file.", NULL);
+	    return TCL_ERROR;
+	 }
 	 break;
      case END_IDX:
 	 fclose(LoggingFile);
@@ -1942,6 +1956,10 @@ _netgen_log(ClientData clientData,
      case RESET_IDX:
 	 fclose(LoggingFile);
 	 LoggingFile = fopen(LogFileName, "w");
+	 if (!LoggingFile) {
+	    Tcl_SetResult(interp, "Could not open log file.", NULL);
+	    return TCL_ERROR;
+	 }
 	 break;
      case SUSPEND_IDX:
 	 fclose(LoggingFile);
@@ -2203,14 +2221,20 @@ _netcmp_compare(ClientData clientData,
   hascontents2 = HasContents(tp2);

   if (hascontents1 && !hascontents2 && (tp2->flags & CELL_PLACEHOLDER)) {
-       Fprintf(stdout, "Circuit 2 cell %s is a black box; will not flatten "
+       Fprintf(stdout, "\nCircuit 2 cell %s is a black box; will not flatten "
                        "Circuit 1\n", name2);
   }
   else if (hascontents2 && !hascontents1 && (tp1->flags & CELL_PLACEHOLDER)) {
-       Fprintf(stdout, "Circuit 1 cell %s is a black box; will not flatten "
+       Fprintf(stdout, "\nCircuit 1 cell %s is a black box; will not flatten "
                        "Circuit 2\n", name1);
   }
-   else if (hascontents1 || hascontents2) {
+   else if (!hascontents1 && !hascontents2 && (tp1->flags & CELL_PLACEHOLDER)
+		&& (tp2->flags & CELL_PLACEHOLDER)) {
+       /* Two empty subcircuits, don't flatten anything */
+       Fprintf(stdout, "\nCircuit 1 cell %s and Circuit 2 cell %s are black"
+			" boxes.\n", name1, name2);
+   }
+   else {
       FlattenUnmatched(tp1, name1, 1, 0);
       FlattenUnmatched(tp2, name2, 1, 0);
       DescribeContents(name1, fnum1, name2, fnum2);
@@ -2479,39 +2503,37 @@ _netcmp_run(ClientData clientData,
 	    ExhaustiveSubdivision = 1;
 	    while (!Iterate() && !InterruptPending);
 	    automorphisms = VerifyMatching();
-	    if (automorphisms == -1)
-	       Fprintf(stdout, "Netlists do not match.\n");
-	    else if (automorphisms == 0)
-	       Fprintf(stdout, "Netlists match uniquely.\n");
-	    else {
+	    if (automorphisms > 0) {
 	       // First try to resolve automorphisms uniquely using
 	       // property matching
 	       automorphisms = ResolveAutomorphsByProperty();
-	       if (automorphisms == 0)
-	          Fprintf(stdout, "Netlists match uniquely.\n");
-	       else if (automorphisms > 0) {
+	       if (automorphisms > 0) {
 	          // Next, attempt to resolve automorphisms uniquely by
 	          // using the pin names
 		  automorphisms = ResolveAutomorphsByPin();
 	       }
-
-	       if (automorphisms == 0)
-	          Fprintf(stdout, "Netlists match uniquely.\n");
-	       else if (automorphisms > 0) {
+	       if (automorphisms > 0) {
 	          // Anything left is truly indistinguishable
-	          Fprintf(stdout, "Netlists match with %d symmetr%s.\n",
-				automorphisms, (automorphisms == 1) ? "y" : "ies");
-
-		  while ((automorphisms = ResolveAutomorphisms()) > 0);
+		  while (ResolveAutomorphisms() > 0);
 	       }
-	       if (automorphisms == -1)
-		  Fprintf(stdout, "Netlists do not match.\n");
-	       else
-		  Fprintf(stdout, "Circuits match correctly.\n");
 	    }
-	    if (PropertyErrorDetected) {
-	       Fprintf(stdout, "There were property errors.\n");
-	       PrintPropertyResults(dolist);
+
+	    if (automorphisms == -1)
+	       Fprintf(stdout, "Netlists do not match.\n");
+	    else if (automorphisms == -2)
+	       Fprintf(stdout, "Netlists match uniquely with port errors.\n");
+	    else {
+	       if (automorphisms == 0)
+	          Fprintf(stdout, "Netlists match uniquely");
+	       else
+	          Fprintf(stdout, "Netlists match with %d symmetr%s",
+				automorphisms, (automorphisms == 1) ? "y" : "ies");
+	       if (PropertyErrorDetected) {
+	          Fprintf(stdout, " with property errors.\n");
+	          PrintPropertyResults(dolist);
+	       }
+	       else
+		  Fprintf(stdout, ".\n");
 	    }
 	    disable_interrupt();
         }
@@ -2529,8 +2551,14 @@ _netcmp_run(ClientData clientData,
 /*		 all, or no option.			*/
 /* Formerly: v						*/
 /* Results:						*/
-/*	For only, equivalent, unique:  Return 1 if 	*/
-/*	verified, zero if not.				*/
+/*	For only, equivalent, unique:  Return 		*/
+/*	 1: verified					*/
+/*	 0: not verified				*/
+/*	-1: no elements or nodes			*/
+/*	-3: verified with property error		*/
+/*   equiv option					*/
+/*	-2: pin mismatch				*/
+/*							*/
 /* Side Effects:					*/
 /*	For options elements, nodes, and all without	*/
 /*	option -list:  Write output to log file.	*/
@@ -2624,13 +2652,21 @@ _netcmp_verify(ClientData clientData,
 	 else
 	     Fprintf(stdout, "Netlists do not match.\n");
      }
+      else if (automorphisms == -2) {
+	 if (index == EQUIV_IDX)
+	    Tcl_SetObjResult(interp, Tcl_NewBooleanObj(1));
+	 else if (index == UNIQUE_IDX)
+	    Tcl_SetObjResult(interp, Tcl_NewIntObj(-2));
+	 else if (index > 0)
+	    Fprintf(stdout, "Circuits match uniquely with port errors.\n");
+      }
      else {
 	 if (automorphisms) {
 	    if (index == EQUIV_IDX)
 	        Tcl_SetObjResult(interp, Tcl_NewIntObj((int)automorphisms));
 	    else if (index == UNIQUE_IDX)
 	        Tcl_SetObjResult(interp, Tcl_NewBooleanObj(0));
-	    else
+	    else if (index > 0)
 	        Printf("Circuits match with %d symmetr%s.\n",
 			automorphisms, (automorphisms == 1) ? "y" : "ies");
 	 }
@@ -2639,11 +2675,13 @@ _netcmp_verify(ClientData clientData,
 		if (PropertyErrorDetected == 0)
 	           Tcl_SetObjResult(interp, Tcl_NewBooleanObj(1));
 	        else
-	           Tcl_SetObjResult(interp, Tcl_NewIntObj(2));
+	           Tcl_SetObjResult(interp, Tcl_NewIntObj(-3));
 	    }
-	    else {
+	    else if (index > 0) {
 	        Fprintf(stdout, "Circuits match uniquely.\n");
-		if (PropertyErrorDetected != 0)
+		if (PropertyErrorDetected == 0)
+		   Fprintf(stdout, ".\n");
+		else
 		   Fprintf(stdout, "Property errors were found.\n");
 	    }
 	 }
@@ -3066,7 +3104,11 @@ _netcmp_equate(ClientData clientData,
 		tp1->flags |= CELL_PLACEHOLDER;
 		tp2->flags |= CELL_PLACEHOLDER;
 	    }
-	    else {
+	    else if (doforce != TRUE) {
+		/* When doforce is TRUE, ElementClass has been set to NULL
+		 * even though circuits contain elements, so this message
+		 * is not correct.
+		 */
 		Fprintf(stdout, "Equate pins:  cell %s and/or %s "
 			"has no elements.\n", name1, name2);
 		/* This is not necessarily an error, so go ahead and match pins. */
@@ -3098,6 +3140,13 @@ _netcmp_equate(ClientData clientData,
 	 else if (result > 0) {
 	    Fprintf(stdout, "Cell pin lists are equivalent.\n");
 	 }
+	 else if (result == -1) {
+	    Fprintf(stdout, "Cell pin lists for %s and %s do not match.\n",
+			name1, name2);
+	 }
+	 else if (result == -2) {
+	    Fprintf(stdout, "Attempt to match empty cell to non-empty cell.\n");
+	 }
 	 else {
 	    Fprintf(stdout, "Cell pin lists for %s and %s altered to match.\n",
 			name1, name2);
@@ -3328,6 +3377,7 @@ _netcmp_equate(ClientData clientData,
 /*	add	  --- add new property			*/
 /*	remove	  --- delete existing property		*/
 /*	tolerance --- set property tolerance		*/
+/*	associate --- associate property with a pin	*/
 /*	merge	  --- (deprecated)			*/
 /* or							*/
 /*	netgen::property default			*/
@@ -3366,11 +3416,11 @@ _netcmp_property(ClientData clientData,

    char *options[] = {
 	"add", "create", "remove", "delete", "tolerance", "merge", "serial",
-	"series", "parallel", NULL
+	"series", "parallel", "associate", NULL
    };
    enum OptionIdx {
 	ADD_IDX, CREATE_IDX, REMOVE_IDX, DELETE_IDX, TOLERANCE_IDX, MERGE_IDX,
-	SERIAL_IDX, SERIES_IDX, PARALLEL_IDX
+	SERIAL_IDX, SERIES_IDX, PARALLEL_IDX, ASSOCIATE_IDX
    };
    int result, index, idx2;

@@ -3793,6 +3843,29 @@ _netcmp_property(ClientData clientData,
 		}
 		break;

+	    case ASSOCIATE_IDX:
+		if (objc == 3) {
+		    Tcl_WrongNumArgs(interp, 1, objv, "{property_key pin_name} ...");
+		    return TCL_ERROR;
+		}
+		for (i = 3; i < objc; i++) {
+		    // Each value must be a duplet
+		    result = Tcl_ListObjLength(interp, objv[i], &llen);
+		    if ((result != TCL_OK) || (llen != 2)) {
+			Tcl_SetResult(interp, "Not a {key pin} pair list.",
+					NULL);
+		    }
+		    else {
+			result = Tcl_ListObjIndex(interp, objv[i], 0, &tobj1);
+			if (result != TCL_OK) return result;
+			result = Tcl_ListObjIndex(interp, objv[i], 1, &tobj2);
+			if (result != TCL_OK) return result;
+			PropertyAssociatePin(tp->name, fnum, Tcl_GetString(tobj1),
+					Tcl_GetString(tobj2));
+		    }
+		}
+		break;
+
 	    case TOLERANCE_IDX:
 		if (objc == 3) {
 		    Tcl_WrongNumArgs(interp, 1, objv, "{property_key tolerance} ...");
Author	SHA1	Message	Date
Tim Edwards	1e1d506697	Merge branch 'master' into netgen-1.5	2022-12-16 02:00:03 -05:00
Tim Edwards	013fff9f37	(1) Fixed the series sorting, which needed to be modified to match the parallel sorting routine. This fixes occasional property errors with series-connected devices such as resistors. (2) Added a method to associate properties with specific pins when pins are permutable. This allows netgen to properly check a value like source/drain area when the definition of source and drain has changed due to permutation of the device. (3) Added a "property" command extension "associate" to associate a property with a pin, for use with the method described in (2).	2022-12-15 21:34:56 -05:00
Tim Edwards	4edaf0813d	Merge branch 'master' into netgen-1.5	2022-11-17 02:00:01 -05:00
Tim Edwards	2292ab813b	Corrected a badly implemented routine that can cause very long run-times on large projects where a lot of cells need to be deleted.	2022-11-16 12:37:05 -05:00
Tim Edwards	a4ae5ed989	Merge branch 'master' into netgen-1.5	2022-11-05 02:00:01 -04:00
Tim Edwards	7e8508db53	Additional correction to the property match subroutine to better check instances with permutable pins when checking parallelized instances with disconnected pins vs. mutually connected pins.	2022-11-04 20:40:37 -04:00
Tim Edwards	c9f7b24e0f	Found an error in property matching causing weird errors in the LVS result. The property matching was failing to match (M=1) to (M!=1) if M was not registered as a property name (which it often isn't). This would allow devices with different numbers of instances in parallel to be put in the same matching group, which then could later identify as a mismatch if the instances were checked in a different order.	2022-11-04 12:07:21 -04:00
Tim Edwards	d850586a14	Merge branch 'master' into netgen-1.5	2022-11-03 02:00:03 -04:00
Tim Edwards	95605ebbd4	Prevented checks from automatically treating two empty cells as black boxes. The check was supposed to check that both empty cells really are black box entries.	2022-11-02 09:48:39 -04:00
Tim Edwards	4b5b117100	Merge branch 'master' into netgen-1.5	2022-11-02 02:00:02 -04:00
Tim Edwards	98e6a4bd8f	Implemented the change from pull request #65 from Mitch Bailey (slightly altered to put the inexpensive flag checks before the more expensive string match).	2022-11-01 13:21:35 -04:00
Tim Edwards	c73d9ec4ff	Updated version to go along with pull request #67 from Mitch Bailey.	2022-11-01 11:44:36 -04:00
D. Mitch Bailey	a5375177c5	parameterized string length and increased to 256 Rebasing over latest commit.	2022-11-01 11:43:43 -04:00
Tim Edwards	935e54abe6	Merge branch 'master' into netgen-1.5	2022-11-01 02:00:02 -04:00
Tim Edwards	27b095754e	Fixed an error that prints bogus property mismatch errors when netgen is supposed to be checking properties for symmetry sorting, but not reporting anything. This causes mysterious property mismatch errors that don't actually exist to show up in the output.	2022-10-31 17:32:15 -04:00
Tim Edwards	49ccf1949a	Merge branch 'master' into netgen-1.5	2022-10-30 02:00:03 -04:00
Tim Edwards	db457c562b	Corrected a problem that is very similar to the last issue, which is that when the "class ignore" command is used, then ports of a parent cell need to be checked for being disconnected if they connect only to ports of an ignored/deleted child cell.	2022-10-29 11:43:01 -04:00
Tim Edwards	9b84776374	Merge branch 'master' into netgen-1.5	2022-10-26 02:00:01 -04:00
Tim Edwards	06386bee1b	Corrected an issue with "flatten": If a cell has disconnected ports, then flattening instances of that cell can cause a port of the parent cell connected to the disconnected port of the child cell to itself become disconnected. If the parent port is not changed to show the disconnected state, then pin mismatch can occur if the netlist being matched didn't have the same flattened subcell. This condition is now detected and handled correctly.	2022-10-25 20:14:44 -04:00
Tim Edwards	2af3f2a3f7	Merge branch 'master' into netgen-1.5	2022-10-25 02:00:01 -04:00
Tim Edwards	7cd8d82964	Fix for an error causing a segfault. This does not fix the underlying issue (which needs to be investigated), but it does prevent netgen from crashing when it encounters it (netgen will generate an erro message instead).	2022-10-24 21:45:14 -04:00
Tim Edwards	738abbdad9	Merge branch 'master' into netgen-1.5	2022-10-01 02:00:01 -04:00
Tim Edwards	3aeea9d164	Re-applied the modifications of revisions 231 and 232, and updated the version to revision 234.	2022-09-30 11:47:36 -04:00
Tim Edwards	12e1ff295f	Revert "Part 2 of folding in Mitch Bailey's code. This part is a" This reverts commit `4fa4d046c8`. Reverting back to before the major change to MatchPins(), which is breaking existing LVS scripts.	2022-09-30 11:36:09 -04:00
Tim Edwards	8d7569e9a3	Merge branch 'master' into netgen-1.5	2022-09-24 02:00:02 -04:00
Tim Edwards	2f9e898ec6	Version updated along with the merge of pull request #62 from Mitch Bailey.	2022-09-23 16:04:49 -04:00
D. Mitch Bailey	9663579dd0	Restore matching circuits if one is empty (but only if pins match).	2022-09-21 08:05:39 -07:00
Tim Edwards	d9425163e1	Merge branch 'master' into netgen-1.5	2022-09-18 02:00:02 -04:00
Tim Edwards	f02e2b1ee0	Handled backslash-escapes (convert "\" to "\\") when writing pins to the JSON format file (since JSON does not allow single backslash characters. Previously nets had been handled correctly, but not pins. Resolves github issue tracker Issue #60 from Proppy.	2022-09-17 14:33:27 -04:00
Tim Edwards	9ba1dfe814	Merge branch 'master' into netgen-1.5	2022-09-17 02:00:02 -04:00
Tim Edwards	cc5f6d929f	Added a missing block of code from Mitch Bailey's version that fails to handle a topology match with a pin mismatch situation.	2022-09-16 13:55:23 -04:00
Tim Edwards	fadd0ae2fc	Merge branch 'master' into netgen-1.5	2022-09-16 02:00:02 -04:00
Tim Edwards	4fa4d046c8	Part 2 of folding in Mitch Bailey's code. This part is a significant overhaul of the MatchPins() code, and better handles issues with pins disconnected from nets and removes cases in which proxy pins are incorrectly generated.	2022-09-15 10:50:52 -04:00
Tim Edwards	153ce0e2b3	Merge branch 'master' into netgen-1.5	2022-09-14 02:00:02 -04:00
Tim Edwards	9297090dc1	Start of merging Mitch Bailey's code changes from github pull request #59 ("Pin match"). Because the pull request has rather sweeping modifications, I am doing this in two steps. The change that most breaks with existing comparison methods is in the PinMatch() routine in netcmp.c, where the method of generating proxy pins has been removed. There are specific cases for which the proxy pin method exists, although these were coping with issues arising from extraction in magic which have been dealt with to some extend. Possibly the proxy pin method is no longer needed. So the PinMatch() changes will be done in a second commit where it's easier to revert or modify the changes without affecting the modifications from this commit.	2022-09-13 10:55:00 -04:00
Tim Edwards	bfdacab28c	Merge branch 'master' into netgen-1.5	2022-09-13 02:00:02 -04:00
Tim Edwards	79e193e0c9	Modified behavior for the "-noflatten" option on LVS: Added a command option "flatten prohibit" (or "flatten deny") to prevent a subcell from being flattened at any time during the compare process. Previously, the "-noflatten" option for the "lvs" script had been used to prevent flattening during initial pre-match, but if the circuit passed the prematch phase and subcells were mismatched, they would be flattened regardless of whether or not they were listed by the "-noflatten" option. This also codifies a way to prevent subcells from being flattened in the setup file rather than in the "lvs" command line. Also: Found and fixed a bug that prevents the use of "-noflatten=" with a cell name or list of cell names instead of a filename.	2022-09-12 11:26:21 -04:00
Tim Edwards	7e9bd9f2a0	Merge branch 'master' into netgen-1.5	2022-06-28 02:00:02 -04:00
Tim Edwards	2056b37c95	Yesterday's commit surfaced two errors in series; this fixes the second one of them, which is a failure to change CurrentTail when an extra (implicit) pin was added to the last component in the current cell, resulting in the failure of Node() to add the new no-connect node, which instead overwrites the pin just created.	2022-06-27 20:35:30 -04:00
Tim Edwards	ee92d880d7	Merge branch 'master' into netgen-1.5	2022-06-27 02:00:01 -04:00
Tim Edwards	7550ef9258	Corrected an error in reworking verilog instances to add pins that were implicit in the first instances but made explicit in a later one. If more than one such implicit pin was handled for the same cell, then the pin count would become wrong and rather unpredictable behavior results.	2022-06-26 22:16:03 -04:00
Tim Edwards	a795981eff	Corrected a prematch issue that will flatten a cell on one side even when the opposing netlist has a black-box entry for the same cell. The black-box entry can't be flattened, so this just results in the cell mysteriously disappearing from one side.	2022-06-26 14:57:25 -04:00
Tim Edwards	d3407b3e56	Merge branch 'master' into netgen-1.5	2022-06-15 02:00:50 -04:00
Tim Edwards	1b6e4e2b36	Corrected an error in the last commit which can cause the pin enumeration in MatchPins() to overflow the cover() array and cause a segmentation fault.	2022-06-14 11:36:30 -04:00
Tim Edwards	0a94bec191	Merge branch 'master' into netgen-1.5	2022-06-13 02:00:18 -04:00
Tim Edwards	edbe5d6e86	Made minor changes to MatchPins() to handle multiple pins connected to a single net (as can be done with assignments in verilog or with zero-voltage sources or zero-value resistors in SPICE). Corrected an error in the SPICE netlist reader that prevented the proper use of zero-voltage sources as net splitters.	2022-06-12 17:25:37 -04:00
Tim Edwards	4a7b6bf22a	Merge branch 'master' into netgen-1.5	2022-06-09 02:00:52 -04:00
Tim Edwards	f8ed4e42e2	Corrected the parsing of verilog netlists to use the right delimiter set when parsing pin names (the correct delimiter set was used in one place but not in another). Extended the pin matching to include the minor hack of ignoring the backslash before backslash-escaped verilog names when there is otherwise no exact match, since many tools convert verilog to SPICE by removing the backslash and trailing space. This avoids pin mismatches in a known set of use cases.	2022-06-08 11:53:47 -04:00
@@ -1 +1 @@
 .5.221
 .5.243