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31 Commits
Author SHA1 Message Date
Tim Edwards d9425163e1 Merge branch 'master' into netgen-1.5 2022-09-18 02:00:02 -04:00
Tim Edwards f02e2b1ee0 Handled backslash-escapes (convert "\" to "\\") when writing pins
to the JSON format file (since JSON does not allow single backslash
characters.  Previously nets had been handled correctly, but not
pins.  Resolves github issue tracker Issue #60 from Proppy.
2022-09-17 14:33:27 -04:00
Tim Edwards 9ba1dfe814 Merge branch 'master' into netgen-1.5 2022-09-17 02:00:02 -04:00
Tim Edwards cc5f6d929f Added a missing block of code from Mitch Bailey's version that
fails to handle a topology match with a pin mismatch situation.
2022-09-16 13:55:23 -04:00
Tim Edwards fadd0ae2fc Merge branch 'master' into netgen-1.5 2022-09-16 02:00:02 -04:00
Tim Edwards 4fa4d046c8 Part 2 of folding in Mitch Bailey's code. This part is a
significant overhaul of the MatchPins() code, and better handles
issues with pins disconnected from nets and removes cases in
which proxy pins are incorrectly generated.
2022-09-15 10:50:52 -04:00
Tim Edwards 153ce0e2b3 Merge branch 'master' into netgen-1.5 2022-09-14 02:00:02 -04:00
Tim Edwards 9297090dc1 Start of merging Mitch Bailey's code changes from github pull
request #59 ("Pin match").  Because the pull request has rather
sweeping modifications, I am doing this in two steps.  The change
that most breaks with existing comparison methods is in the
PinMatch() routine in netcmp.c, where the method of generating
proxy pins has been removed.  There are specific cases for which
the proxy pin method exists, although these were coping with
issues arising from extraction in magic which have been dealt
with to some extend.  Possibly the proxy pin method is no longer
needed.  So the PinMatch() changes will be done in a second
commit where it's easier to revert or modify the changes without
affecting the modifications from this commit.
2022-09-13 10:55:00 -04:00
Tim Edwards bfdacab28c Merge branch 'master' into netgen-1.5 2022-09-13 02:00:02 -04:00
Tim Edwards 79e193e0c9 Modified behavior for the "-noflatten" option on LVS: Added a
command option "flatten prohibit" (or "flatten deny") to prevent
a subcell from being flattened at any time during the compare
process.  Previously, the "-noflatten" option for the "lvs"
script had been used to prevent flattening during initial
pre-match, but if the circuit passed the prematch phase and
subcells were mismatched, they would be flattened regardless of
whether or not they were listed by the "-noflatten" option.  This
also codifies a way to prevent subcells from being flattened in
the setup file rather than in the "lvs" command line.  Also:
Found and fixed a bug that prevents the use of "-noflatten=" with
a cell name or list of cell names instead of a filename.
2022-09-12 11:26:21 -04:00
Tim Edwards 7e9bd9f2a0 Merge branch 'master' into netgen-1.5 2022-06-28 02:00:02 -04:00
Tim Edwards 2056b37c95 Yesterday's commit surfaced two errors in series; this fixes the
second one of them, which is a failure to change CurrentTail when
an extra (implicit) pin was added to the last component in the
current cell, resulting in the failure of Node() to add the new
no-connect node, which instead overwrites the pin just created.
2022-06-27 20:35:30 -04:00
Tim Edwards ee92d880d7 Merge branch 'master' into netgen-1.5 2022-06-27 02:00:01 -04:00
Tim Edwards 7550ef9258 Corrected an error in reworking verilog instances to add pins that
were implicit in the first instances but made explicit in a later
one.  If more than one such implicit pin was handled for the same
cell, then the pin count would become wrong and rather unpredictable
behavior results.
2022-06-26 22:16:03 -04:00
Tim Edwards a795981eff Corrected a prematch issue that will flatten a cell on one side
even when the opposing netlist has a black-box entry for the same
cell.  The black-box entry can't be flattened, so this just
results in the cell mysteriously disappearing from one side.
2022-06-26 14:57:25 -04:00
Tim Edwards d3407b3e56 Merge branch 'master' into netgen-1.5 2022-06-15 02:00:50 -04:00
Tim Edwards 1b6e4e2b36 Corrected an error in the last commit which can cause the pin
enumeration in MatchPins() to overflow the cover() array and
cause a segmentation fault.
2022-06-14 11:36:30 -04:00
Tim Edwards 0a94bec191 Merge branch 'master' into netgen-1.5 2022-06-13 02:00:18 -04:00
Tim Edwards edbe5d6e86 Made minor changes to MatchPins() to handle multiple pins connected
to a single net (as can be done with assignments in verilog or with
zero-voltage sources or zero-value resistors in SPICE).  Corrected
an error in the SPICE netlist reader that prevented the proper use
of zero-voltage sources as net splitters.
2022-06-12 17:25:37 -04:00
Tim Edwards 4a7b6bf22a Merge branch 'master' into netgen-1.5 2022-06-09 02:00:52 -04:00
Tim Edwards f8ed4e42e2 Corrected the parsing of verilog netlists to use the right
delimiter set when parsing pin names (the correct delimiter set
was used in one place but not in another).  Extended the pin
matching to include the minor hack of ignoring the backslash
before backslash-escaped verilog names when there is otherwise
no exact match, since many tools convert verilog to SPICE by
removing the backslash and trailing space.  This avoids pin
mismatches in a known set of use cases.
2022-06-08 11:53:47 -04:00
Tim Edwards 661c9ee854 Merge branch 'master' into netgen-1.5 2022-04-16 02:00:16 -04:00
Tim Edwards 89ef83c597 Corrected an error in the verilog parser that incorrectly handles
the syntax "assign a = b" when both a and b are vectors (but no
vector delimiters appear in the assignment).
2022-04-15 14:13:11 -04:00
Tim Edwards 4e96c84ec6 Extended the method created in the last commit so that it properly
handles both operator order of precedence and parenthetical groups
including nested groups.
2022-04-15 12:19:48 -04:00
Tim Edwards 5b21c1be3a Merge branch 'master' into netgen-1.5 2022-04-15 02:00:16 -04:00
Tim Edwards 592c16706e Extended the verilog parsing to parse definitions such that nested
definitions are handled correctly.  Also:  Added code to evaluate
simple expressions for array bounds.  Previously the parser could
handle a value followed by "+" or "-" and a constant.  Now it can
handle all basic arithmetic.
2022-04-14 22:33:58 -04:00
Tim Edwards e11dbac384 Merge branch 'master' into netgen-1.5 2022-01-17 03:00:14 -05:00
Tim Edwards bfb01e032f Implemented another change discussed in netgen github issue #47
by Anton Blanchard, which prevents the double-loop in the
PropertyOptimize() routine from continuing the outer loop if
all devices in the run have already been merged.
2022-01-16 14:47:52 -05:00
Tim Edwards d0ec17e442 Implemented a change to the way that netgen generates the subcircuit
summary, so that the summary lists the total number of devices as well
as the number of devices after parallel optimization, in the form
"device_name (M->N)", where "M" is the total number of devices, and
"N" is the number of devices after parallel combination.  This makes
the output somewhat more meaningful to the end user.  Implementation
as discussed in github issue #47.
2022-01-16 14:16:30 -05:00
Tim Edwards 0535128421 Merge branch 'master' into netgen-1.5 2022-01-16 03:00:18 -05:00
Tim Edwards 6195745b45 Modified the parallel combination code so that properties of
parallel devices are prepended rather than appended, which avoids
having to search for the end of what may be a rapidly increasing
linked list of properties.  This reduces the amount of time spent
in the parallel combination code.  Thanks to Anton Blanchard for
pointing out this inefficiency.
2022-01-15 12:06:43 -05:00
9 changed files with 1041 additions and 711 deletions
+1 -1
View File
@@ -1 +1 @@
1.5.217
1.5.232
+68 -19
View File
@@ -66,9 +66,13 @@ void flattenCell(char *name, int file)
else
ThisCell = LookupCellFile(name, file);
if (ThisCell == NULL) {
Printf("No cell %s found.\n", name);
Printf("No cell %s (%d) found.\n", name, file);
return;
}
/* Placeholder cells must not be flattened */
if (ThisCell->flags & CELL_PLACEHOLDER) return;
FreeNodeNames(ThisCell);
ParentParams = ThisCell->cell;
@@ -278,16 +282,20 @@ int flattenInstancesOf(char *name, int fnum, char *instance)
}
else {
if (Debug)
Printf("Flattening instances of %s within cell: %s\n", instance, name);
Printf("Flattening instances of %s within cell: %s (%d)\n", instance,
name, fnum);
if (fnum == -1)
ThisCell = LookupCell(name);
else
ThisCell = LookupCellFile(name, fnum);
if (ThisCell == NULL) {
Printf("No cell %s found.\n", name);
Printf("No cell %s (%d) found.\n", name, fnum);
return 0;
}
}
/* Placeholder cells must not be flattened */
if (ThisCell->flags & CELL_PLACEHOLDER) return 0;
FreeNodeNames(ThisCell);
ParentParams = ThisCell->cell;
@@ -681,7 +689,7 @@ void convertGlobalsOf(char *name, int fnum, char *instance)
else
ThisCell = LookupCellFile(name, fnum);
if (ThisCell == NULL) {
Printf("No cell %s found.\n", name);
Printf("No cell %s (%d) found.\n", name, fnum);
return;
}
}
@@ -1111,7 +1119,7 @@ int UniquePins(char *name, int filenum)
ThisCell = LookupCellFile(name, filenum);
if (ThisCell == NULL) {
Printf("No cell %s found.\n", name);
Printf("No cell %s (%d) found.\n", name, filenum);
return 0;
}
@@ -1128,12 +1136,33 @@ int UniquePins(char *name, int filenum)
firstport = (struct objlist **)CALLOC(maxnode + 1, sizeof(struct objlist *));
portcount = FIRSTPIN;
lob = NULL;
for (ob = ThisCell->cell; ob != NULL; ob = ob->next) {
if (ob->type != PORT) break;
if (ob->node > 0) {
nodecount[ob->node]++;
if (nodecount[ob->node] == 2) {
Printf("Duplicate pin %s in cell %s\n", ob->name, ThisCell->name);
if (!(*matchfunc)(firstport[ob->node]->name, ob->name)) {
Printf("Pins %s and %s are shorted in cell %s (%d)\n", ob->name,
firstport[ob->node]->name, ThisCell->name, ThisCell->file);
/* Do not count this as a duplicate pin. */
nodecount[ob->node]--;
/* Move the pin adjacent to the one it is shorted to (if it
* isn't already); this will make the work of MatchPins() easier.
*/
if (firstport[ob->node]->next != ob) {
lob->next = ob->next;
ob->next = firstport[ob->node]->next;
firstport[ob->node]->next = ob;
ob = lob;
}
lob = ob;
continue;
}
else {
Printf("Duplicate pin %s in cell %s (%d)\n", ob->name,
ThisCell->name, filenum);
}
}
if (nodecount[ob->node] > 1) {
/* Remove this node; prep for removal by marking with UNKNOWN */
@@ -1148,6 +1177,7 @@ int UniquePins(char *name, int filenum)
}
}
portcount++;
lob = ob;
}
if (needscleanup)
@@ -1332,7 +1362,7 @@ int CleanupPins(char *name, int filenum)
ThisCell = LookupCellFile(name, filenum);
if (ThisCell == NULL) {
Printf("No cell %s found.\n", name);
Printf("No cell %s (%d) found.\n", name, filenum);
return 0;
}
@@ -1599,19 +1629,22 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
}
}
if (match) {
if (ecomp->cell1 && (ecomp->num1 > 0)) {
if (ecomp->cell1 && (ecomp->num1 > 0) &&
(!(ecomp->cell1->flags & CELL_PLACEHOLDER))) {
Fprintf(stdout, "Flattening instances of %s in cell %s (%d)"
" makes a better match\n", ecomp->cell1->name,
name1, file1);
flattenInstancesOf(name1, file1, ecomp->cell1->name);
modified++;
}
if (ecomp->cell2 && (ecomp->num2 > 0)) {
if (ecomp->cell2 && (ecomp->num2 > 0) &&
(!(ecomp->cell2->flags & CELL_PLACEHOLDER))) {
Fprintf(stdout, "Flattening instances of %s in cell %s (%d)"
" makes a better match\n", ecomp->cell2->name,
name2, file2);
flattenInstancesOf(name2, file2, ecomp->cell2->name);
modified++;
}
modified++;
}
/* Reset or apply the count adjustments */
@@ -1688,13 +1721,21 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
}
}
if (match) {
if (ecomp->cell2) {
Fprintf(stdout, "Flattening instances of %s in cell %s (%d)"
/* Don't flatten if cell1 is a black box, because it */
/* can't also be flattened. */
if ((ecomp->num1 == 0) || (ecomp->cell1->class !=
CLASS_MODULE)) {
if (ecomp->cell2 && !(ecomp->cell2->flags & CELL_PLACEHOLDER)) {
Fprintf(stdout, "Flattening instances of %s in cell %s (%d)"
" makes a better match\n", ecomp->cell2->name,
name2, file2);
flattenInstancesOf(name2, file2, ecomp->cell2->name);
flattenInstancesOf(name2, file2, ecomp->cell2->name);
modified++;
}
}
modified++;
}
/* Reset or apply the count adjustments */
@@ -1718,7 +1759,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
}
/* Case 3: Cell1 class is a subcircuit, and flattening */
/* it (without regard to cell1) improves the matching. */
/* it (without regard to cell2) improves the matching. */
else if ((ecomp->num1 != ecomp->num2) && (ecomp->cell1 != NULL) &&
(ecomp->num1 != 0) && (ecomp->cell1->class == CLASS_SUBCKT)) {
@@ -1746,13 +1787,21 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
}
}
if (match) {
if (ecomp->cell1) {
Fprintf(stdout, "Flattening instances of %s in cell %s (%d)"
/* Don't flatten if cell2 is a black box, because it */
/* can't also be flattened. */
if ((ecomp->num2 == 0) || (ecomp->cell2->class !=
CLASS_MODULE)) {
if (ecomp->cell1 && !(ecomp->cell1->flags & CELL_PLACEHOLDER)) {
Fprintf(stdout, "Flattening instances of %s in cell %s (%d)"
" makes a better match\n", ecomp->cell1->name,
name1, file1);
flattenInstancesOf(name1, file1, ecomp->cell1->name);
flattenInstancesOf(name1, file1, ecomp->cell1->name);
modified++;
}
}
modified++;
}
/* Reset or apply the count adjustments */
+389 -364
View File
File diff suppressed because it is too large Load Diff
+73 -63
View File
@@ -331,77 +331,87 @@ int GetNextLineNoNewline(char *delimiter)
linetok = (char *)MALLOC(linesize + 1);
}
/* Check for substitutions (verilog only). Make sure linetok is */
/* large enough to hold the entire line after substitutions. */
if (definitions != NULL) {
char *s, *w, e;
struct property *kl;
int len, dlen, vlen, addin = 0;
unsigned char found = FALSE;
for (s = line; *s != '\0'; s++) {
if (*s == '`') {
w = s + 1;
while (isalnum(*w) || (*w == '_') || (*w == '$')) w++;
e = *w;
*w = '\0';
kl = (struct property *)HashLookup(s + 1, definitions);
if (kl != NULL) {
dlen = strlen(s);
if (kl->type == PROP_STRING) {
vlen = strlen(kl->pdefault.string);
}
else vlen = 12; /* Leave room for numeric conversion */
addin += vlen - dlen + 1;
found = TRUE;
}
*w = e;
}
}
if (found) {
len = strlen(line);
if (len + addin > linesize) {
while (len + addin > linesize) linesize += 500;
FREE(linetok);
linetok = (char *)MALLOC(linesize);
}
}
}
/* Make definition substitutions (verilog only) */
if (definitions != NULL) {
if (definitions == NULL)
strcpy(linetok, line);
else {
char *s, *t, *w, e;
struct property *kl;
int len, dlen, vlen, addin = 0;
int oldlinesize = linesize;
unsigned char found = TRUE;
t = linetok;
for (s = line; *s != '\0'; s++) {
if (*s == '`') {
w = s + 1;
while (isalnum(*w) || (*w == '_') || (*w == '$')) w++;
e = *w;
*w = '\0';
kl = (struct property *)HashLookup(s + 1, definitions);
if (kl != NULL) {
if (kl->type == PROP_STRING)
strcpy(t, kl->pdefault.string);
else if (kl->type == PROP_INTEGER)
sprintf(t, "%d", kl->pdefault.ival);
else if (kl->type == PROP_DOUBLE)
sprintf(t, "%g", kl->pdefault.dval);
t += strlen(t);
s = w - 1;
/* Check for substitutions (verilog only). Make sure linetok is */
/* large enough to hold the entire line after substitutions. */
while (found) { /* Do this recursively, for nested definitions */
found = FALSE;
for (s = line; *s != '\0'; s++) {
if (*s == '`') {
w = s + 1;
while (isalnum(*w) || (*w == '_') || (*w == '$')) w++;
e = *w;
*w = '\0';
kl = (struct property *)HashLookup(s + 1, definitions);
if (kl != NULL) {
dlen = strlen(s);
if (kl->type == PROP_STRING) {
vlen = strlen(kl->pdefault.string);
}
else vlen = 12; /* Leave room for numeric conversion */
addin += vlen - dlen + 1;
found = TRUE;
}
*w = e;
}
}
if (found) {
len = strlen(line);
if (len + addin > linesize) {
while (len + addin > linesize) linesize += 500;
FREE(linetok);
linetok = (char *)MALLOC(linesize);
}
}
/* Make definition substitutions (verilog only) */
t = linetok;
for (s = line; *s != '\0'; s++) {
if (*s == '`') {
w = s + 1;
while (isalnum(*w) || (*w == '_') || (*w == '$')) w++;
e = *w;
*w = '\0';
kl = (struct property *)HashLookup(s + 1, definitions);
if (kl != NULL) {
if (kl->type == PROP_STRING)
strcpy(t, kl->pdefault.string);
else if (kl->type == PROP_INTEGER)
sprintf(t, "%d", kl->pdefault.ival);
else if (kl->type == PROP_DOUBLE)
sprintf(t, "%g", kl->pdefault.dval);
t += strlen(t);
s = w - 1;
}
else *t++ = *s;
*w = e;
}
else *t++ = *s;
*w = e;
}
*t = '\0';
/* Copy substituted linetok back to line and repeat until */
/* there are no more substitutions to be made. */
if (oldlinesize != linesize) {
FREE(line);
line = (char *)MALLOC(linesize + 501);
oldlinesize = linesize;
}
else *t++ = *s;
strcpy(line, linetok);
}
*t = '\0';
}
else
strcpy(linetok, line);
TrimQuoted(linetok);
linenum++;
+20 -24
View File
@@ -3337,16 +3337,13 @@ int CombineParallel(char *model, int file)
/* "sob" to it. If "ob" does not have properties, then */
/* create a property record and set property "M" to 1. */
/* Find last non-property record of sob ( = pob) */
/* Find first property record of sob ( = spropfirst) */
/* Find last property record of sob ( = sproplast) */
/* Find last non-property record of sob ( = pob) */
/* Find first property record of sob ( = spropfirst) */
spropfirst = sproplast = NULL;
spropfirst = NULL;
for (ob2 = sob; ob2->type > FIRSTPIN || ob2 == sob; ob2 = ob2->next)
pob = ob2;
if (ob2->type == PROPERTY) spropfirst = ob2;
for (; ob2->type == PROPERTY; ob2 = ob2->next)
sproplast = ob2;
if (spropfirst == NULL) {
/* Create new property instance record if one doesn't exist */
@@ -3372,8 +3369,9 @@ int CombineParallel(char *model, int file)
nob->next = pob->next;
pob->next = nob;
/* Handle case of contiguous entries */
if (lob == pob) lob = nob;
spropfirst = sproplast = nob;
spropfirst = nob;
}
if (propfirst == NULL) {
/* Create new property instance record if one doesn't exist */
@@ -3396,27 +3394,26 @@ int CombineParallel(char *model, int file)
kv->type = PROP_ENDLIST;
kv->value.ival = 0;
/* Append to sob's property list */
nob->next = sproplast->next;
sproplast->next = nob;
if (lob == sproplast) lob = nob;
/* Prepend to sob's property list */
nob->next = pob->next;
pob->next = nob;
/* Handle case of contiguous entries */
if (lob == pob) lob = nob;
}
if (propfirst != NULL) {
else {
// Series/Parallel logic:
// If propfirst has _tag in properties,
// then add an "open" tag at propfirst
add_prop_tag(propfirst, '(');
// If spropfirst has _tag in properties,
// then add an "open" tag at spropfirst
add_prop_tag(spropfirst, '(');
// if spropfirst has _tag in properties then add an "open" tag
// to spropfirst and a "close" tag to propfirst
if (add_prop_tag(spropfirst, '(')) add_prop_tag(propfirst, ')');
// if propfirst has _tag in properties then add an "open" tag
// to propfirst and a "close" tag to spropfirst
if (add_prop_tag(propfirst, '(')) add_prop_tag(spropfirst, ')');
/* Append ob's property list to sob */
proplast->next = sproplast->next;
sproplast->next = propfirst;
if (lob == sproplast) lob = proplast;
/* Prepend ob's property list to sob */
proplast->next = pob->next;
pob->next = propfirst;
}
/* Link up around object to be removed */
@@ -3429,7 +3426,6 @@ int CombineParallel(char *model, int file)
obr = nob;
}
dcnt++;
}
FREE((char *)pstr);
}
+15 -2
View File
@@ -1449,7 +1449,20 @@ skip_ends:
if (LookupObject(pos, CurrentCell) == NULL) Node(pos);
if (LookupObject(neg, CurrentCell) == NULL) Node(neg);
/* Any device properties? */
/* Get voltage value (if present); save as property "value" */
if (nexttok != NULL) {
if (matchnocase(nexttok, "DC")) {
SpiceTokNoNewline();
}
}
if (nexttok != NULL) {
if (StringIsValueOrExpression(nexttok)) {
AddProperty(&kvlist, "value", nexttok);
}
}
/* Any other device properties? */
while (nexttok != NULL)
{
SpiceTokNoNewline();
@@ -1477,7 +1490,7 @@ skip_ends:
else if (CountPorts(model, filenum) != 2) {
/* Modeled device: Make sure it has the right number of ports */
Fprintf(stderr, "Device \"%s\" has wrong number of ports for a "
"voltage source.\n");
"voltage source.\n", inst);
goto baddevice;
}
Cell(instname, model, pos, neg);
+286 -120
View File
@@ -60,6 +60,7 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
// See netfile.c for explanation of delimiters. 'X'
// separates single-character delimiters from two-character delimiters.
#define VLOG_DELIMITERS "X///**/#((**)X,;:(){}[]="
#define VLOG_EQUATION_DELIMITERS "X///**/#((**)X,;:(){}[]=+-*/"
#define VLOG_PIN_NAME_DELIMITERS "X///**/(**)X()"
#define VLOG_PIN_CHECK_DELIMITERS "X///**/(**)X,;(){}"
@@ -71,6 +72,8 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
struct hashdict verilogparams;
// Global storage for verilog definitions
struct hashdict verilogdefs;
// Record file pointer that is associated with the hash tables
int hashfile = -1;
// Global storage for wire buses
struct hashdict buses;
@@ -127,6 +130,187 @@ char *strvchr(char *string, char c)
return NULL;
}
/* Linked list, much like tokstack in netgen.c, but much simpler. */
/* contents are either a value, if oper = 0, or an operator. */
struct expr_stack {
int value;
char oper;
struct expr_stack *next;
struct expr_stack *last;
};
//-------------------------------------------------------------------------
// Evaluate an expression for an array bound. This is much like
// ReduceOneExpression() in netgen.c, but only handles basic integer
// arithmetic (+,-,*,/) and grouping by parentheses.
//
// Returns 1 if successful, 0 on error.
// Evaluated result is placed in the integer pointed to by "valptr".
//-------------------------------------------------------------------------
int EvalExpr(struct expr_stack **stackptr, int *valptr)
{
struct expr_stack *texp, *start, *tmp, *stack;
int modified, value;
stack = *stackptr;
/* Most expressions are going to be just one number, so treat
* that as a special case.
*/
if ((stack->oper == '\0') && (stack->last == NULL)) {
*valptr = stack->value;
FREE(stack);
*stackptr = NULL;
return 1;
}
/* Move to the end of the stack, which is the beginning of the
* expression.
*/
for (start = stack; start->last; start = start->last);
/* Run passes until no more modifications can be made */
modified = TRUE;
while (modified == TRUE) {
modified = FALSE;
/* Find any + or - that is used as a sign of a value */
for (texp = start; texp; texp = texp->next) {
if ((texp->oper == '+') || (texp->oper == '-') || (texp->oper == '*') ||
(texp->oper == '/') || (texp->oper == '(')) {
if ((texp->next != NULL) && (texp->next->next != NULL) &&
(texp->next->next->oper == '\0')) {
if (texp->next->oper == '+') {
/* Remove the unnecessary sign */
tmp = texp->next;
texp->next = tmp->next;
tmp->next->last = texp;
FREE(tmp);
modified = TRUE;
}
else if (texp->next->oper == '-') {
/* Remove the sign and negate the value */
tmp = texp->next;
texp->next->next->value = -texp->next->next->value;
texp->next = tmp->next;
tmp->next->last = texp;
FREE(tmp);
modified = TRUE;
}
}
}
}
/* Reduce (a * b) and (a / b) */
for (texp = start; texp; texp = texp->next) {
if ((texp->last != NULL) && (texp->next != NULL) && (texp->oper != '\0')) {
if ((texp->last->oper == '\0') && (texp->next->oper == '\0')) {
if (texp->oper == '*') {
/* Multiply */
texp->last->value *= texp->next->value;
/* Remove two items from the stack */
tmp = texp;
texp = texp->last;
texp->next = tmp->next->next;
if (tmp->next->next) tmp->next->next->last = texp;
FREE(tmp->next);
FREE(tmp);
modified = TRUE;
}
if (texp->oper == '/') {
/* Divide */
texp->last->value /= texp->next->value;
/* Remove two items from the stack */
tmp = texp;
texp = texp->last;
texp->next = tmp->next->next;
if (tmp->next->next) tmp->next->next->last = texp;
FREE(tmp->next);
FREE(tmp);
modified = TRUE;
}
}
}
}
/* Reduce (a + b) and (a - b) */
for (texp = start; texp; texp = texp->next) {
if ((texp->last != NULL) && (texp->next != NULL) && (texp->oper != '\0')) {
if ((texp->last->oper == '\0') && (texp->next->oper == '\0')) {
if (texp->oper == '-') {
/* Subtract */
texp->last->value -= texp->next->value;
/* Remove two items from the stack */
tmp = texp;
texp = texp->last;
texp->next = tmp->next->next;
if (tmp->next->next) tmp->next->next->last = texp;
FREE(tmp->next);
FREE(tmp);
modified = TRUE;
}
if (texp->oper == '+') {
/* Add */
texp->last->value += texp->next->value;
/* Remove two items from the stack */
tmp = texp;
texp = texp->last;
texp->next = tmp->next->next;
if (tmp->next->next) tmp->next->next->last = texp;
FREE(tmp->next);
FREE(tmp);
modified = TRUE;
}
}
}
}
/* Reduce (a) */
for (texp = start; texp; texp = texp->next) {
if ((texp->last != NULL) && (texp->next != NULL) && (texp->oper == '\0')) {
if ((texp->last->oper == '(') && (texp->next->oper == ')')) {
tmp = texp->last;
texp->last->oper = '\0';
texp->last->value = texp->value;
texp->last->next = texp->next->next;
if (texp->next->next) texp->next->next->last = texp->last;
FREE(texp->next);
FREE(texp);
texp = tmp;
modified = TRUE;
}
}
}
}
/* If only one numerical item remains, then place it in valptr and return 1 */
texp = start;
if ((texp->oper == '\0') && (texp->next == NULL)) {
*valptr = texp->value;
FREE(texp);
*stackptr = NULL;
return 1;
}
/* Clean up the stack before returning error status */
while (texp) {
tmp = texp;
texp = texp->next;
FREE(tmp);
}
*stackptr = NULL;
return 0;
}
//-------------------------------------------------------------------------
// Get bus indexes from the notation name[a:b]. If there is only "name"
// then look up the name in the bus hash list and return the index bounds.
@@ -138,147 +322,123 @@ char *strvchr(char *string, char c)
int GetBusTok(struct bus *wb)
{
int result, start, end;
int result, start, end, value;
char oper;
struct property *kl = NULL;
struct expr_stack *stack, *newexp;
if (wb == NULL) return 0;
else {
wb->start = -1;
wb->end = -1;
}
wb->start = -1;
wb->end = -1;
stack = NULL;
/* Parse a value for array bounds [a : b], including possible use */
/* of parameters, definitions, and basic arithmetic. */
if (match(nexttok, "[")) {
SkipTokComments(VLOG_DELIMITERS);
result = sscanf(nexttok, "%d", &start);
if (result != 1) {
char *aptr = NULL;
char addin;
// Check for "+/-(n)" at end of a parameter name
aptr = strrchr(nexttok, '+');
if (aptr == NULL) aptr = strrchr(nexttok, '-');
if (aptr != NULL) {
addin = *aptr;
*aptr = '\0';
}
// Is name in the parameter list?
kl = (struct property *)HashLookup(nexttok, &verilogparams);
if (kl == NULL) {
Printf("Array value %s is not a number or a parameter.\n",
nexttok);
return 1;
}
else {
if (kl->type == PROP_STRING) {
result = sscanf(kl->pdefault.string, "%d", &start);
if (result != 1) {
Printf("Parameter %s has value %s that cannot be parsed"
" as an integer.\n", nexttok, kl->pdefault.string);
return 1;
}
}
else if (kl->type == PROP_INTEGER) {
start = kl->pdefault.ival;
}
else if (kl->type == PROP_DOUBLE) {
start = (int)kl->pdefault.dval;
if ((double)start != kl->pdefault.dval) {
Printf("Parameter %s has value %g that cannot be parsed"
" as an integer.\n", nexttok, kl->pdefault.dval);
return 1;
}
}
else {
Printf("Parameter %s has unknown type; don't know how"
" to parse.\n", nexttok);
start = end = -1;
oper = '\0';
while (nexttok) {
SkipTokComments(VLOG_EQUATION_DELIMITERS);
if (match(nexttok, "]")) {
result = 1;
if (stack == NULL) {
Printf("Empty array found.\n");
return 1;
}
}
if (aptr != NULL) {
int addval;
*aptr = addin;
if (sscanf(aptr + 1, "%d", &addval) != 1) {
Printf("Unable to parse parameter increment '%s'\n", aptr);
if (EvalExpr(&stack, &end) != 1) {
Printf("Bad expression found in array.\n");
return 1;
}
start += (addin == '+') ? addval : -addval;
if (start == -1) start = end; // Single bit
break;
}
}
SkipTokComments(VLOG_DELIMITERS);
if (match(nexttok, "]")) {
result = 1;
end = start; // Single bit
}
else if (!match(nexttok, ":")) {
Printf("Badly formed array notation: Expected colon, found %s\n", nexttok);
return 1;
}
else {
SkipTokComments(VLOG_DELIMITERS);
result = sscanf(nexttok, "%d", &end);
if (result != 1) {
char *aptr = NULL;
char addin;
// Check for "+/-(n)" at end of a parameter name
aptr = strrchr(nexttok, '+');
if (aptr == NULL) aptr = strrchr(nexttok, '-');
if (aptr != NULL) {
addin = *aptr;
*aptr = '\0';
if (match(nexttok, ":")) {
if (stack == NULL) {
Printf("Empty array start found.\n");
return 1;
}
if (EvalExpr(&stack, &start) != 1) {
Printf("Bad expression found in array.\n");
return 1;
}
continue;
}
else if (match(nexttok, "+") || match(nexttok, "-")
|| match(nexttok, "*") || match(nexttok, "/")
|| match(nexttok, "(") || match(nexttok, ")")) {
newexp = (struct expr_stack *)MALLOC(sizeof(struct expr_stack));
newexp->oper = *nexttok;
newexp->value = 0;
newexp->next = NULL;
newexp->last = stack;
if (stack) stack->next = newexp;
stack = newexp;
continue;
}
if ((result = sscanf(nexttok, "%d", &value)) != 1) {
// Is name in the parameter list?
kl = (struct property *)HashLookup(nexttok, &verilogparams);
kl = (struct property *)HashLookup(nexttok, &verilogparams);
if (kl == NULL) {
Printf("Array value %s is not a number or a parameter.\n",
nexttok);
return 1;
nexttok);
value = 0;
break;
}
else {
if (kl->type == PROP_STRING) {
result = sscanf(kl->pdefault.string, "%d", &end);
result = sscanf(kl->pdefault.string, "%d", &value);
if (result != 1) {
Printf("Parameter %s has value %s that cannot be parsed"
" as an integer.\n", nexttok,
kl->pdefault.string);
return 1;
" as an integer.\n",
nexttok, kl->pdefault.string);
value = 0;
break;
}
}
else if (kl->type == PROP_INTEGER) {
end = kl->pdefault.ival;
value = kl->pdefault.ival;
}
else if (kl->type == PROP_DOUBLE) {
end = (int)kl->pdefault.dval;
if ((double)end != kl->pdefault.dval) {
Printf("Cannot parse second digit from parameter "
"%s value %g\n", nexttok, kl->pdefault.dval);
return 1;
value = (int)kl->pdefault.dval;
if ((double)value != kl->pdefault.dval) {
Printf("Parameter %s has value %g that cannot be parsed"
" as an integer.\n",
nexttok, kl->pdefault.dval);
value = 0;
break;
}
}
else {
Printf("Parameter %s has unknown type; don't know how"
" to parse.\n", nexttok);
return 1;
Printf("Parameter %s has unknown type; don't know how"
" to parse.\n", nexttok);
value = 0;
break;
}
}
if (aptr != NULL) {
int addval;
*aptr = addin;
if (sscanf(aptr + 1, "%d", &addval) != 1) {
Printf("Unable to parse parameter increment '%s'\n", aptr);
return 1;
}
end += (addin == '+') ? addval : -addval;
}
}
newexp = (struct expr_stack *)MALLOC(sizeof(struct expr_stack));
newexp->oper = '\0';
newexp->value = value;
newexp->next = NULL;
newexp->last = stack;
if (stack) stack->next = newexp;
stack = newexp;
}
wb->start = start;
wb->end = end;
/* In case of error, stack may need cleaning up */
while (stack != NULL) {
newexp = stack;
stack = stack->last;
FREE(newexp);
}
while (!match(nexttok, "]")) {
SkipTokComments(VLOG_DELIMITERS);
if (nexttok == NULL) {
@@ -1128,13 +1288,6 @@ skip_endmodule:
kl->pdefault.ival = 1;
kl->slop.ival = 0;
}
else if (nexttok[0] == '(') {
/* For now, the netgen verilog parser doesn't handle `define f(X) ... */
SkipNewLine(VLOG_DELIMITERS);
FREE(kl->key);
FREE(kl);
kl = NULL;
}
else if (ConvertStringToInteger(nexttok, &ival) == 1) {
/* Parameter parses as an integer */
kl->type = PROP_INTEGER;
@@ -1319,6 +1472,8 @@ skip_endmodule:
rhs = LookupObject(assignname, CurrentCell);
*aptr = '[';
}
else
strcpy(assignroot, nexttok);
}
else {
j = -1;
@@ -1514,7 +1669,7 @@ nextinst:
// Read the pin list
while (nexttok != NULL) {
SkipTokComments(VLOG_DELIMITERS);
SkipTokComments(VLOG_PIN_CHECK_DELIMITERS);
if (match(nexttok, ")")) break;
else if (match(nexttok, ",")) continue;
@@ -2073,6 +2228,9 @@ nextinst:
obptr->next = nobj;
HashPtrInstall(nobj->name, nobj, &(CurrentCell->objdict));
/* Ensure that CurrentTail is correct */
if (obptr == CurrentTail) CurrentTail = nobj;
if (LookupObject(scan->net, CurrentCell) == NULL)
Node(scan->net);
join(scan->net, nobj->name);
@@ -2114,6 +2272,7 @@ nextinst:
}
}
}
obptr = obptr->next;
}
else {
Fprintf(stderr, "Error: Instance %s has pin %s which is "
@@ -2212,8 +2371,19 @@ char *ReadVerilogTop(char *fname, int *fnum, int blackbox)
hashfunc = hashcase;
}
InitializeHashTable(&verilogparams, OBJHASHSIZE);
InitializeHashTable(&verilogdefs, OBJHASHSIZE);
if ((hashfile != -1) && (hashfile != *fnum)) {
/* Started a new file, so remove all the parameters and definitions */
RecurseHashTable(&verilogparams, freeprop);
HashKill(&verilogparams);
RecurseHashTable(&verilogdefs, freeprop);
HashKill(&verilogdefs);
hashfile = -1;
}
if (hashfile == -1) {
InitializeHashTable(&verilogparams, OBJHASHSIZE);
InitializeHashTable(&verilogdefs, OBJHASHSIZE);
hashfile = *fnum;
}
definitions = &verilogdefs;
/* Add the pre-defined key "LVS" to verilogdefs */
@@ -2233,10 +2403,6 @@ char *ReadVerilogTop(char *fname, int *fnum, int blackbox)
// Cleanup
while (CellStack != NULL) PopStack(&CellStack);
RecurseHashTable(&verilogparams, freeprop);
HashKill(&verilogparams);
RecurseHashTable(&verilogdefs, freeprop);
HashKill(&verilogdefs);
definitions = (struct hashdict *)NULL;
// Record the top level file.
+110 -86
View File
@@ -62,16 +62,18 @@ proc netgen::convert_to_json {filename lvs_final} {
puts $fjson " \["
set cktval [lindex $value 0]
foreach pin [lrange $cktval 0 end-1] {
puts $fjson " \"$pin\","
set pinstr [string map {"\\" "\\\\"} $pin]
puts $fjson " \"$pinstr\","
}
set pin [lindex $cktval end]
set pin [string map {"\\" "\\\\"} [lindex $cktval end]]
puts $fjson " \"$pin\""
puts $fjson " \], \["
set cktval [lindex $value 1]
foreach pin [lrange $cktval 0 end-1] {
puts $fjson " \"$pin\","
set pinstr [string map {"\\" "\\\\"} $pin]
puts $fjson " \"$pinstr\","
}
set pin [lindex $cktval end]
set pin [string map {"\\" "\\\\"} [lindex $cktval end]]
puts $fjson " \"$pin\""
puts $fjson " \]"
if {$kidx == $nkeys} {
@@ -393,7 +395,7 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
# If argument is a filename then read the list of cells from it;
# otherwise, argument is the list of files itself in quotes or
# braces.
if {![catch {file exists $value}]} {
if {[file exists $value]} {
if {![catch {open $value r} fnf]} {
while {[gets $fnf line] >= 0} {
if {[lindex $line 0] != "#"} {
@@ -532,14 +534,24 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
}
set properr {}
set matcherr {}
set pinsgood -1
set childMismatch 0 ;# 1 indicates black-box child subcircuit mismatch
while {$endval != {}} {
if {$dolist == 1} {
netgen::run -list converge
} else {
netgen::run converge
}
netgen::log echo on
set pinMismatch 0 ;# indicates pin mismatch in top cell
set doCheckFlatten 0
set doFlatten 0
if {[netgen::print queue] == {}} {
set doEquatePins 1 ;# run equate pins on top cell
} else {
set doEquatePins 0 ;# don't run equate pins unless unique match
}
set forceMatch 0 ;# for pin matching
netgen::log echo off
if {[verify equivalent]} {
# Resolve automorphisms by pin and property
if {$dolist == 1} {
@@ -548,96 +560,105 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
netgen::run resolve
}
set uresult [verify unique]
# uresult: -3 : unique with property error
# -2 : equivalent with port errors
# -1 : black box
# 0 : equivalent but not unique
# 1 : unique
if {$uresult == 0} {
netgen::log echo on
netgen::log put " Networks match locally but not globally.\n"
netgen::log put " Probably connections are swapped.\n"
netgen::log put " Check the end of logfile ${logfile} for implicated nodes.\n"
netgen::log echo off
if {$dolist == 1} {
verify -list nodes
} else {
verify nodes
}
# Flatten the non-matching subcircuit (but not the top-level cells)
if {[netgen::print queue] != {}} {
if {([lsearch $noflat [lindex $endval 0]] == -1) &&
([lsearch $noflat [lindex $endval 1]] == -1)} {
netgen::log put " Flattening non-matched subcircuits $endval\n"
netgen::flatten class "[lindex $endval 0] $fnum1"
netgen::flatten class "[lindex $endval 1] $fnum2"
} else {
netgen::log put " Continuing with black-boxed subcircuits $endval\n"
lappend matcherr [lindex $endval 0]"($fnum1)"
lappend matcherr [lindex $endval 1]"($fnum2)"
# Match pins
netgen::log echo off
if {$dolist == 1} {
set result [equate -list -force pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
} else {
set result [equate -force pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
}
if {$result != 0} {
equate classes "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"
}
set pinsgood $result
netgen::log echo on
}
}
set doCheckFlatten 1
} else {
netgen::log echo off
if {$dolist == 1} {
set result [equate -list pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
} else {
set result [equate pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
}
if {$result != 0} {
equate classes "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"
}
# If $uresult == -1 then these are black-box entries and
# $pinsgood should not be set to the resulting value.
if {$uresult > 0} {
set pinsgood $result
}
netgen::log echo on
# Equate pins for black boxes, unique matches (possibly with property
# errors), and unique with port errors
set doEquatePins 1
}
if {$uresult == -1} { ;# black box
set forceMatch 1
} elseif {$uresult == -3} { ;# property error
lappend properr [lindex $endval 0]
} elseif {$uresult == -2} { ;# unmatched pins
set doCheckFlatten 1
}
if {$uresult == 2} {lappend properr [lindex $endval 0]}
} else {
# Flatten the non-matching subcircuit (but not the top-level cells)
if {[netgen::print queue] != {}} {
# not equivalent
netgen::log echo on
# netgen::log put " DEBUG: not equivalent $endval\n"
netgen::log echo off
set doCheckFlatten 1
}
if {$doCheckFlatten} {
# Flatten the non-matching subcircuit (but not the top-level cell,
# or cells explicitly prohibited from flattening)
if {[netgen::print queue] != {}} {
if {([lsearch $noflat [lindex $endval 0]] == -1) &&
([lsearch $noflat [lindex $endval 1]] == -1)} {
netgen::log put " Flattening non-matched subcircuits $endval\n"
netgen::flatten class "[lindex $endval 0] $fnum1"
netgen::flatten class "[lindex $endval 1] $fnum2"
} else {
([lsearch $noflat [lindex $endval 1]] == -1)} {
set doFlatten 1
} else {
netgen::log echo on
netgen::log put " Continuing with black-boxed subcircuits $endval\n"
netgen::log echo off
lappend matcherr [lindex $endval 0]"($fnum1)"
lappend matcherr [lindex $endval 0]"($fnum2)"
# Match pins
netgen::log echo off
if {$dolist == 1} {
set result [equate -list -force pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
} else {
set result [equate -force pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
}
if {$result != 0} {
equate classes "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"
}
set pinsgood $result
netgen::log echo on
lappend matcherr [lindex $endval 1]"($fnum2)"
netgen::flatten prohibit "[lindex $endval 0] $fnum1"
netgen::flatten prohibit "[lindex $endval 1] $fnum2"
set doEquatePins 1
set childMismatch 1
set forceMatch 1
}
}
}
netgen::log echo off
if {$doEquatePins} {
# Match pins
if {$dolist == 1} {
if {$forceMatch} {
set result [equate -list -force pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
} else {
set result [equate -list pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
}
} else {
if {$forceMatch} {
set result [equate -force pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
} else {
set result [equate pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
}
}
if {$result >= 0} {
equate classes "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"
}
# Do not set pinMismatch for black boxes
if {$result < 0} {
if {$result == -1 && [netgen::print queue] != {} && $forceMatch != 1} {
# flatten pin mismatch, but not empty cells (-2) or top cell or
# cells prohibited from flattening.
set doFlatten 1
}
} elseif {[netgen::print queue] == {} && $result == 0} {
set pinMismatch 1
}
}
if {$doFlatten} {
netgen::log echo on
netgen::log put " Flattening non-matched subcircuits $endval\n"
netgen::log echo off
netgen::flatten class "[lindex $endval 0] $fnum1"
netgen::flatten class "[lindex $endval 1] $fnum2"
}
if {$dolist == 1} {
catch {lappend lvs_final $lvs_out}
set lvs_out {}
@@ -646,20 +667,23 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
set endval [netgen::compare hierarchical]
}
}
netgen::log echo off
puts stdout "Result: " nonewline
netgen::log echo on
if {$pinsgood == 0} {
# NOTE: Need to disambiguate these two cases. . .
netgen::log put "Cells failed matching, or top level cell failed pin matching.\n"
netgen::log put "\nFinal result: "
if {$pinMismatch || $childMismatch} {
if {$childMismatch} {
netgen::log put "Subcell(s) failed matching.\n"
}
if {$pinMismatch} {
netgen::log put "Top level cell failed pin matching.\n"
}
} else {
verify only
}
if {$properr != {}} {
netgen::log put "The following cells had property errors:\n " [regsub -all { } $properr "\n "] "\n"
netgen::log put "\nThe following cells had property errors:\n " [regsub -all { } $properr "\n "] "\n"
}
if {$matcherr != {}} {
netgen::log put "The following subcells failed to match:\n " [regsub -all { } $matcherr "\n "] "\n"
netgen::log put "\nThe following subcells failed to match:\n " [regsub -all { } $matcherr "\n "] "\n"
}
if {$dolog} {
netgen::log end
+79 -32
View File
@@ -1056,6 +1056,12 @@ _netgen_flatten(ClientData clientData,
FlattenInstancesOf(repstr, filenum);
}
}
else if (!strcmp(argv, "prohibit") || !strcmp(argv, "deny")) {
tp = GetTopCell(filenum);
Printf("Will not flatten instances of %s in file %s\n", repstr, tp->name);
/* Mark cell as placeholder so it will not be flattened */
tp->flags |= CELL_PLACEHOLDER;
}
else {
Tcl_WrongNumArgs(interp, 1, objv, "class valid_cellname");
return TCL_ERROR;
@@ -1931,9 +1937,17 @@ _netgen_log(ClientData clientData,
switch(index) {
case START_IDX:
LoggingFile = fopen(LogFileName, "w");
if (!LoggingFile) {
Tcl_SetResult(interp, "Could not open log file.", NULL);
return TCL_ERROR;
}
break;
case RESUME_IDX:
LoggingFile = fopen(LogFileName, "a");
if (!LoggingFile) {
Tcl_SetResult(interp, "Could not open log file.", NULL);
return TCL_ERROR;
}
break;
case END_IDX:
fclose(LoggingFile);
@@ -1942,6 +1956,10 @@ _netgen_log(ClientData clientData,
case RESET_IDX:
fclose(LoggingFile);
LoggingFile = fopen(LogFileName, "w");
if (!LoggingFile) {
Tcl_SetResult(interp, "Could not open log file.", NULL);
return TCL_ERROR;
}
break;
case SUSPEND_IDX:
fclose(LoggingFile);
@@ -2203,11 +2221,11 @@ _netcmp_compare(ClientData clientData,
hascontents2 = HasContents(tp2);
if (hascontents1 && !hascontents2 && (tp2->flags & CELL_PLACEHOLDER)) {
Fprintf(stdout, "Circuit 2 cell %s is a black box; will not flatten "
Fprintf(stdout, "\nCircuit 2 cell %s is a black box; will not flatten "
"Circuit 1\n", name2);
}
else if (hascontents2 && !hascontents1 && (tp1->flags & CELL_PLACEHOLDER)) {
Fprintf(stdout, "Circuit 1 cell %s is a black box; will not flatten "
Fprintf(stdout, "\nCircuit 1 cell %s is a black box; will not flatten "
"Circuit 2\n", name1);
}
else if (hascontents1 || hascontents2) {
@@ -2223,6 +2241,10 @@ _netcmp_compare(ClientData clientData,
DescribeContents(name1, fnum1, name2, fnum2);
}
}
else { /* Two empty subcircuits */
Fprintf(stdout, "\nCircuit 1 cell %s and Circuit 2 cell %s are black"
" boxes.\n", name1, name2);
}
CreateTwoLists(name1, fnum1, name2, fnum2, dolist);
// Return the names of the two cells being compared, if doing "compare
@@ -2479,39 +2501,37 @@ _netcmp_run(ClientData clientData,
ExhaustiveSubdivision = 1;
while (!Iterate() && !InterruptPending);
automorphisms = VerifyMatching();
if (automorphisms == -1)
Fprintf(stdout, "Netlists do not match.\n");
else if (automorphisms == 0)
Fprintf(stdout, "Netlists match uniquely.\n");
else {
if (automorphisms > 0) {
// First try to resolve automorphisms uniquely using
// property matching
automorphisms = ResolveAutomorphsByProperty();
if (automorphisms == 0)
Fprintf(stdout, "Netlists match uniquely.\n");
else if (automorphisms > 0) {
if (automorphisms > 0) {
// Next, attempt to resolve automorphisms uniquely by
// using the pin names
automorphisms = ResolveAutomorphsByPin();
}
if (automorphisms == 0)
Fprintf(stdout, "Netlists match uniquely.\n");
else if (automorphisms > 0) {
if (automorphisms > 0) {
// Anything left is truly indistinguishable
Fprintf(stdout, "Netlists match with %d symmetr%s.\n",
automorphisms, (automorphisms == 1) ? "y" : "ies");
while ((automorphisms = ResolveAutomorphisms()) > 0);
while (ResolveAutomorphisms() > 0);
}
if (automorphisms == -1)
Fprintf(stdout, "Netlists do not match.\n");
else
Fprintf(stdout, "Circuits match correctly.\n");
}
if (PropertyErrorDetected) {
Fprintf(stdout, "There were property errors.\n");
PrintPropertyResults(dolist);
if (automorphisms == -1)
Fprintf(stdout, "Netlists do not match.\n");
else if (automorphisms == -2)
Fprintf(stdout, "Netlists match uniquely with port errors.\n");
else {
if (automorphisms == 0)
Fprintf(stdout, "Netlists match uniquely");
else
Fprintf(stdout, "Netlists match with %d symmetr%s",
automorphisms, (automorphisms == 1) ? "y" : "ies");
if (PropertyErrorDetected) {
Fprintf(stdout, " with property errors.\n");
PrintPropertyResults(dolist);
}
else
Fprintf(stdout, ".\n");
}
disable_interrupt();
}
@@ -2529,8 +2549,14 @@ _netcmp_run(ClientData clientData,
/* all, or no option. */
/* Formerly: v */
/* Results: */
/* For only, equivalent, unique: Return 1 if */
/* verified, zero if not. */
/* For only, equivalent, unique: Return */
/* 1: verified */
/* 0: not verified */
/* -1: no elements or nodes */
/* -3: verified with property error */
/* equiv option */
/* -2: pin mismatch */
/* */
/* Side Effects: */
/* For options elements, nodes, and all without */
/* option -list: Write output to log file. */
@@ -2624,13 +2650,21 @@ _netcmp_verify(ClientData clientData,
else
Fprintf(stdout, "Netlists do not match.\n");
}
else if (automorphisms == -2) {
if (index == EQUIV_IDX)
Tcl_SetObjResult(interp, Tcl_NewBooleanObj(1));
else if (index == UNIQUE_IDX)
Tcl_SetObjResult(interp, Tcl_NewIntObj(-2));
else if (index > 0)
Fprintf(stdout, "Circuits match uniquely with port errors.\n");
}
else {
if (automorphisms) {
if (index == EQUIV_IDX)
Tcl_SetObjResult(interp, Tcl_NewIntObj((int)automorphisms));
else if (index == UNIQUE_IDX)
Tcl_SetObjResult(interp, Tcl_NewBooleanObj(0));
else
else if (index > 0)
Printf("Circuits match with %d symmetr%s.\n",
automorphisms, (automorphisms == 1) ? "y" : "ies");
}
@@ -2639,11 +2673,13 @@ _netcmp_verify(ClientData clientData,
if (PropertyErrorDetected == 0)
Tcl_SetObjResult(interp, Tcl_NewBooleanObj(1));
else
Tcl_SetObjResult(interp, Tcl_NewIntObj(2));
Tcl_SetObjResult(interp, Tcl_NewIntObj(-3));
}
else {
else if (index > 0) {
Fprintf(stdout, "Circuits match uniquely.\n");
if (PropertyErrorDetected != 0)
if (PropertyErrorDetected == 0)
Fprintf(stdout, ".\n");
else
Fprintf(stdout, "Property errors were found.\n");
}
}
@@ -3066,7 +3102,11 @@ _netcmp_equate(ClientData clientData,
tp1->flags |= CELL_PLACEHOLDER;
tp2->flags |= CELL_PLACEHOLDER;
}
else {
else if (doforce != TRUE) {
/* When doforce is TRUE, ElementClass has been set to NULL
* even though circuits contain elements, so this message
* is not correct.
*/
Fprintf(stdout, "Equate pins: cell %s and/or %s "
"has no elements.\n", name1, name2);
/* This is not necessarily an error, so go ahead and match pins. */
@@ -3098,6 +3138,13 @@ _netcmp_equate(ClientData clientData,
else if (result > 0) {
Fprintf(stdout, "Cell pin lists are equivalent.\n");
}
else if (result == -1) {
Fprintf(stdout, "Cell pin lists for %s and %s do not match.\n",
name1, name2);
}
else if (result == -2) {
Fprintf(stdout, "Attempt to match empty cell to non-empty cell.\n");
}
else {
Fprintf(stdout, "Cell pin lists for %s and %s altered to match.\n",
name1, name2);