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51 Commits
Author SHA1 Message Date
Tim Edwards 2af3f2a3f7 Merge branch 'master' into netgen-1.5 2022-10-25 02:00:01 -04:00
Tim Edwards 7cd8d82964 Fix for an error causing a segfault. This does not fix the
underlying issue (which needs to be investigated), but it does
prevent netgen from crashing when it encounters it (netgen will
generate an erro message instead).
2022-10-24 21:45:14 -04:00
Tim Edwards 738abbdad9 Merge branch 'master' into netgen-1.5 2022-10-01 02:00:01 -04:00
Tim Edwards 3aeea9d164 Re-applied the modifications of revisions 231 and 232, and updated
the version to revision 234.
2022-09-30 11:47:36 -04:00
Tim Edwards 12e1ff295f Revert "Part 2 of folding in Mitch Bailey's code. This part is a"
This reverts commit 4fa4d046c8.

Reverting back to before the major change to MatchPins(), which is
breaking existing LVS scripts.
2022-09-30 11:36:09 -04:00
Tim Edwards 8d7569e9a3 Merge branch 'master' into netgen-1.5 2022-09-24 02:00:02 -04:00
Tim Edwards 2f9e898ec6 Version updated along with the merge of pull request #62 from
Mitch Bailey.
2022-09-23 16:04:49 -04:00
D. Mitch Bailey 9663579dd0 Restore matching circuits if one is empty (but only if pins match). 2022-09-21 08:05:39 -07:00
Tim Edwards d9425163e1 Merge branch 'master' into netgen-1.5 2022-09-18 02:00:02 -04:00
Tim Edwards f02e2b1ee0 Handled backslash-escapes (convert "\" to "\\") when writing pins
to the JSON format file (since JSON does not allow single backslash
characters.  Previously nets had been handled correctly, but not
pins.  Resolves github issue tracker Issue #60 from Proppy.
2022-09-17 14:33:27 -04:00
Tim Edwards 9ba1dfe814 Merge branch 'master' into netgen-1.5 2022-09-17 02:00:02 -04:00
Tim Edwards cc5f6d929f Added a missing block of code from Mitch Bailey's version that
fails to handle a topology match with a pin mismatch situation.
2022-09-16 13:55:23 -04:00
Tim Edwards fadd0ae2fc Merge branch 'master' into netgen-1.5 2022-09-16 02:00:02 -04:00
Tim Edwards 4fa4d046c8 Part 2 of folding in Mitch Bailey's code. This part is a
significant overhaul of the MatchPins() code, and better handles
issues with pins disconnected from nets and removes cases in
which proxy pins are incorrectly generated.
2022-09-15 10:50:52 -04:00
Tim Edwards 153ce0e2b3 Merge branch 'master' into netgen-1.5 2022-09-14 02:00:02 -04:00
Tim Edwards 9297090dc1 Start of merging Mitch Bailey's code changes from github pull
request #59 ("Pin match").  Because the pull request has rather
sweeping modifications, I am doing this in two steps.  The change
that most breaks with existing comparison methods is in the
PinMatch() routine in netcmp.c, where the method of generating
proxy pins has been removed.  There are specific cases for which
the proxy pin method exists, although these were coping with
issues arising from extraction in magic which have been dealt
with to some extend.  Possibly the proxy pin method is no longer
needed.  So the PinMatch() changes will be done in a second
commit where it's easier to revert or modify the changes without
affecting the modifications from this commit.
2022-09-13 10:55:00 -04:00
Tim Edwards bfdacab28c Merge branch 'master' into netgen-1.5 2022-09-13 02:00:02 -04:00
Tim Edwards 79e193e0c9 Modified behavior for the "-noflatten" option on LVS: Added a
command option "flatten prohibit" (or "flatten deny") to prevent
a subcell from being flattened at any time during the compare
process.  Previously, the "-noflatten" option for the "lvs"
script had been used to prevent flattening during initial
pre-match, but if the circuit passed the prematch phase and
subcells were mismatched, they would be flattened regardless of
whether or not they were listed by the "-noflatten" option.  This
also codifies a way to prevent subcells from being flattened in
the setup file rather than in the "lvs" command line.  Also:
Found and fixed a bug that prevents the use of "-noflatten=" with
a cell name or list of cell names instead of a filename.
2022-09-12 11:26:21 -04:00
Tim Edwards 7e9bd9f2a0 Merge branch 'master' into netgen-1.5 2022-06-28 02:00:02 -04:00
Tim Edwards 2056b37c95 Yesterday's commit surfaced two errors in series; this fixes the
second one of them, which is a failure to change CurrentTail when
an extra (implicit) pin was added to the last component in the
current cell, resulting in the failure of Node() to add the new
no-connect node, which instead overwrites the pin just created.
2022-06-27 20:35:30 -04:00
Tim Edwards ee92d880d7 Merge branch 'master' into netgen-1.5 2022-06-27 02:00:01 -04:00
Tim Edwards 7550ef9258 Corrected an error in reworking verilog instances to add pins that
were implicit in the first instances but made explicit in a later
one.  If more than one such implicit pin was handled for the same
cell, then the pin count would become wrong and rather unpredictable
behavior results.
2022-06-26 22:16:03 -04:00
Tim Edwards a795981eff Corrected a prematch issue that will flatten a cell on one side
even when the opposing netlist has a black-box entry for the same
cell.  The black-box entry can't be flattened, so this just
results in the cell mysteriously disappearing from one side.
2022-06-26 14:57:25 -04:00
Tim Edwards d3407b3e56 Merge branch 'master' into netgen-1.5 2022-06-15 02:00:50 -04:00
Tim Edwards 1b6e4e2b36 Corrected an error in the last commit which can cause the pin
enumeration in MatchPins() to overflow the cover() array and
cause a segmentation fault.
2022-06-14 11:36:30 -04:00
Tim Edwards 0a94bec191 Merge branch 'master' into netgen-1.5 2022-06-13 02:00:18 -04:00
Tim Edwards edbe5d6e86 Made minor changes to MatchPins() to handle multiple pins connected
to a single net (as can be done with assignments in verilog or with
zero-voltage sources or zero-value resistors in SPICE).  Corrected
an error in the SPICE netlist reader that prevented the proper use
of zero-voltage sources as net splitters.
2022-06-12 17:25:37 -04:00
Tim Edwards 4a7b6bf22a Merge branch 'master' into netgen-1.5 2022-06-09 02:00:52 -04:00
Tim Edwards f8ed4e42e2 Corrected the parsing of verilog netlists to use the right
delimiter set when parsing pin names (the correct delimiter set
was used in one place but not in another).  Extended the pin
matching to include the minor hack of ignoring the backslash
before backslash-escaped verilog names when there is otherwise
no exact match, since many tools convert verilog to SPICE by
removing the backslash and trailing space.  This avoids pin
mismatches in a known set of use cases.
2022-06-08 11:53:47 -04:00
Tim Edwards 661c9ee854 Merge branch 'master' into netgen-1.5 2022-04-16 02:00:16 -04:00
Tim Edwards 89ef83c597 Corrected an error in the verilog parser that incorrectly handles
the syntax "assign a = b" when both a and b are vectors (but no
vector delimiters appear in the assignment).
2022-04-15 14:13:11 -04:00
Tim Edwards 4e96c84ec6 Extended the method created in the last commit so that it properly
handles both operator order of precedence and parenthetical groups
including nested groups.
2022-04-15 12:19:48 -04:00
Tim Edwards 5b21c1be3a Merge branch 'master' into netgen-1.5 2022-04-15 02:00:16 -04:00
Tim Edwards 592c16706e Extended the verilog parsing to parse definitions such that nested
definitions are handled correctly.  Also:  Added code to evaluate
simple expressions for array bounds.  Previously the parser could
handle a value followed by "+" or "-" and a constant.  Now it can
handle all basic arithmetic.
2022-04-14 22:33:58 -04:00
Tim Edwards e11dbac384 Merge branch 'master' into netgen-1.5 2022-01-17 03:00:14 -05:00
Tim Edwards bfb01e032f Implemented another change discussed in netgen github issue #47
by Anton Blanchard, which prevents the double-loop in the
PropertyOptimize() routine from continuing the outer loop if
all devices in the run have already been merged.
2022-01-16 14:47:52 -05:00
Tim Edwards d0ec17e442 Implemented a change to the way that netgen generates the subcircuit
summary, so that the summary lists the total number of devices as well
as the number of devices after parallel optimization, in the form
"device_name (M->N)", where "M" is the total number of devices, and
"N" is the number of devices after parallel combination.  This makes
the output somewhat more meaningful to the end user.  Implementation
as discussed in github issue #47.
2022-01-16 14:16:30 -05:00
Tim Edwards 0535128421 Merge branch 'master' into netgen-1.5 2022-01-16 03:00:18 -05:00
Tim Edwards 6195745b45 Modified the parallel combination code so that properties of
parallel devices are prepended rather than appended, which avoids
having to search for the end of what may be a rapidly increasing
linked list of properties.  This reduces the amount of time spent
in the parallel combination code.  Thanks to Anton Blanchard for
pointing out this inefficiency.
2022-01-15 12:06:43 -05:00
Tim Edwards afe0e9f758 Merge branch 'master' into netgen-1.5 2022-01-01 03:00:43 -05:00
Tim Edwards 68ec2b2a7c Modified two print statements to change "%s(%d)" to "%s (%d)" as
is my typographic preference.
2021-12-31 13:30:13 -05:00
Tim Edwards ca49a90ed6 Merged changes from github issue #45 from Mitch Bailey. These changes
speed up the time needed to flatten an instance, and add clarity to the
output by specifying the file number for each cell name being modified
during the pre-match stage.
2021-12-31 12:13:11 -05:00
Tim Edwards e487890641 Merge branch 'master' into netgen-1.5 2021-12-31 03:00:42 -05:00
Tim Edwards e07a5b416a Removed lvs_manager.py, which is a derived file and should not have
ended up in the repository, as pointed out by Mitch Bailey in github
issue #44.  Added lvs_manager.py to .gitignore to prevent that from
happening again in the future.
2021-12-30 09:19:44 -05:00
Tim Edwards bb44d3f827 Merge branch 'master' into netgen-1.5 2021-12-30 03:00:43 -05:00
Tim Edwards 8094740048 Corrected a problem that stems from code that was deprecated and
marked as unneeded, so I simply removed the code rather than
debug the issue, which was that buses got the delimeters erased
for checking but never put back again.  Also:  Modified the verilog
reading code so that if an empty set "()" is given for a pin, then
the initial proxy, which is a single net with the name prefix
"_noconnect_", can be promoted to a bus if further processing
reveals it to be a bus and not a single-bit signal.
2021-12-29 14:31:38 -05:00
Tim Edwards c25c4e1160 Merge branch 'master' into netgen-1.5 2021-12-27 03:00:18 -05:00
Tim Edwards a026d37f11 Corrected a place in the verilog read routine where ob->next is
used when ob may be NULL.  Added a check in front for ob == NULL.
Also:  Changed the disconnected node alert so that it does not
mention nodes marked "port_mismatch_error".  These are disconnected
by definition, will show up in the pin list, and printing them as
"disconnected pins" is just confusing to the end user.
2021-12-26 10:31:48 -05:00
Tim Edwards 8ed4e3cf38 Merge branch 'master' into netgen-1.5 2021-12-20 03:00:02 -05:00
Tim Edwards ab614b63f7 Corrected the last commit (again) because FlattenUnmatched()
should not be called after CreateTwoLists().  CreateTwoLists()
was being called in one case only to print the contents of the
cells, so that part was pulled out into a separate routine.
2021-12-19 16:25:32 -05:00
Tim Edwards 83dce151d8 Made a correction to the last commit. The "FlattenUnmatched()"
routine does not have an exact equivalent in PrematchLists() and
needs to be run beforehand.  This fix keeps FlattenUnmatched()
from being run on all cells at the beginning and restricts it
to being run on the contents of individual cells during matching,
after checking if either of the cells is a black-box.  Avoiding
flattening contents of one side when the other is a black-box
(or simply doesn't contain any subcircuits or devices) prevents
unnecessary flattening of cells that will never get compared.
2021-12-17 20:31:41 -05:00
13 changed files with 1027 additions and 566 deletions
+1
View File
@@ -7,6 +7,7 @@ config.log
scripts/config.log
config.status
scripts/config.status
python/lvs_manager.py
*.o
*.so
*~
+1 -1
View File
@@ -1 +1 @@
1.5.212
1.5.235
+117 -80
View File
@@ -66,9 +66,13 @@ void flattenCell(char *name, int file)
else
ThisCell = LookupCellFile(name, file);
if (ThisCell == NULL) {
Printf("No cell %s found.\n", name);
Printf("No cell %s (%d) found.\n", name, file);
return;
}
/* Placeholder cells must not be flattened */
if (ThisCell->flags & CELL_PLACEHOLDER) return;
FreeNodeNames(ThisCell);
ParentParams = ThisCell->cell;
@@ -278,16 +282,20 @@ int flattenInstancesOf(char *name, int fnum, char *instance)
}
else {
if (Debug)
Printf("Flattening instances of %s within cell: %s\n", instance, name);
Printf("Flattening instances of %s within cell: %s (%d)\n", instance,
name, fnum);
if (fnum == -1)
ThisCell = LookupCell(name);
else
ThisCell = LookupCellFile(name, fnum);
if (ThisCell == NULL) {
Printf("No cell %s found.\n", name);
Printf("No cell %s (%d) found.\n", name, fnum);
return 0;
}
}
/* Placeholder cells must not be flattened */
if (ThisCell->flags & CELL_PLACEHOLDER) return 0;
FreeNodeNames(ThisCell);
ParentParams = ThisCell->cell;
@@ -372,22 +380,16 @@ int flattenInstancesOf(char *name, int fnum, char *instance)
/* update node numbers in child to unique numbers */
oldmax = 0;
for (tmp = ChildStart; tmp != NULL; tmp = tmp->next)
for (tmp = ChildStart; tmp != NULL; tmp = tmp->next) {
if (tmp->node > oldmax) oldmax = tmp->node;
if (nextnode <= oldmax) nextnode = oldmax + 1;
for (tmp = ChildStart; tmp != NULL; tmp = tmp->next)
if (tmp->node <= oldmax && tmp->node > 0) {
if (Debug) Printf("Update node %d --> %d\n", tmp->node, nextnode);
UpdateNodeNumbers(ChildStart, tmp->node, nextnode);
nextnode++;
}
if (tmp->node > 0) tmp->node += (nextnode - 1);
}
nextnode += oldmax;
/* copy nodenumbers of ports from parent */
ob2 = ParentParams;
for (tmp = ChildStart; tmp != NULL; tmp = tmp->next) {
if (IsPort(tmp)) {
if (tmp->node > 0) {
for (tmp = ChildStart; tmp && IsPort(tmp); tmp = tmp->next) {
if (tmp->node > 0) {
if (ob2->node == -1) {
// Before commiting to attaching to a unconnected node, see
@@ -413,17 +415,16 @@ int flattenInstancesOf(char *name, int fnum, char *instance)
Printf("Update node %d --> %d\n", tmp->node, ob2->node);
}
UpdateNodeNumbers(ChildStart, tmp->node, ob2->node);
}
}
/* in pathological cases, the lengths of the port lists may
* change. This is an error, but that is no reason to allow
* the code to core dump. We avoid this by placing a
* superfluous check on ob2->type
*/
if (ob2 != NULL) ob2 = ob2->next;
/* in pathological cases, the lengths of the port lists may
* change. This is an error, but that is no reason to allow
* the code to core dump. We avoid this by placing a
* superfluous check on ob2->type
*/
if (ob2 != NULL) ob2 = ob2->next;
if (ob2 == NULL) break;
}
if (ob2 == NULL) break;
}
/* Using name == NULL to indicate that a .ext file is being */
@@ -688,7 +689,7 @@ void convertGlobalsOf(char *name, int fnum, char *instance)
else
ThisCell = LookupCellFile(name, fnum);
if (ThisCell == NULL) {
Printf("No cell %s found.\n", name);
Printf("No cell %s (%d) found.\n", name, fnum);
return;
}
}
@@ -1118,7 +1119,7 @@ int UniquePins(char *name, int filenum)
ThisCell = LookupCellFile(name, filenum);
if (ThisCell == NULL) {
Printf("No cell %s found.\n", name);
Printf("No cell %s (%d) found.\n", name, filenum);
return 0;
}
@@ -1135,12 +1136,33 @@ int UniquePins(char *name, int filenum)
firstport = (struct objlist **)CALLOC(maxnode + 1, sizeof(struct objlist *));
portcount = FIRSTPIN;
lob = NULL;
for (ob = ThisCell->cell; ob != NULL; ob = ob->next) {
if (ob->type != PORT) break;
if (ob->node > 0) {
nodecount[ob->node]++;
if (nodecount[ob->node] == 2) {
Printf("Duplicate pin %s in cell %s\n", ob->name, ThisCell->name);
if (!(*matchfunc)(firstport[ob->node]->name, ob->name)) {
Printf("Pins %s and %s are shorted in cell %s (%d)\n", ob->name,
firstport[ob->node]->name, ThisCell->name, ThisCell->file);
/* Do not count this as a duplicate pin. */
nodecount[ob->node]--;
/* Move the pin adjacent to the one it is shorted to (if it
* isn't already); this will make the work of MatchPins() easier.
*/
if (firstport[ob->node]->next != ob) {
lob->next = ob->next;
ob->next = firstport[ob->node]->next;
firstport[ob->node]->next = ob;
ob = lob;
}
lob = ob;
continue;
}
else {
Printf("Duplicate pin %s in cell %s (%d)\n", ob->name,
ThisCell->name, filenum);
}
}
if (nodecount[ob->node] > 1) {
/* Remove this node; prep for removal by marking with UNKNOWN */
@@ -1155,6 +1177,7 @@ int UniquePins(char *name, int filenum)
}
}
portcount++;
lob = ob;
}
if (needscleanup)
@@ -1339,7 +1362,7 @@ int CleanupPins(char *name, int filenum)
ThisCell = LookupCellFile(name, filenum);
if (ThisCell == NULL) {
Printf("No cell %s found.\n", name);
Printf("No cell %s (%d) found.\n", name, filenum);
return 0;
}
@@ -1421,11 +1444,27 @@ typedef struct ecomplist {
ECompListPtr next;
} ECompList;
/*----------------------------------------------------------------------*/
/* Determine if a cell contains at least one device or subcircuit */
/*----------------------------------------------------------------------*/
int
HasContents(struct nlist *tc)
{
struct objlist *ob;
for (ob = tc->cell; ob; ob = ob->next)
if (ob->type == FIRSTPIN)
return TRUE;
return FALSE;
}
/*------------------------------------------------------*/
/* Survey the contents of a cell and sort into a hash */
/*------------------------------------------------------*/
int
void
SurveyCell(struct nlist *tc, struct hashdict *compdict, int file1, int file2, int which)
{
struct objlist *ob;
@@ -1433,12 +1472,10 @@ SurveyCell(struct nlist *tc, struct hashdict *compdict, int file1, int file2, in
ECompare *ecomp, *qcomp, *ncomp;
int file = (which == 0) ? file1 : file2;
int ofile = (which == 0) ? file2 : file1;
int retval = FALSE;
char *dstr;
for (ob = tc->cell; ob; ob = ob->next) {
if (ob->type == FIRSTPIN) {
retval = TRUE; /* Cell has at least one device or subcircuit */
tsub = LookupCellFile(ob->model.class, file);
if (tsub->flags & CELL_DUPLICATE) {
// Always register a duplicate under the original name
@@ -1492,7 +1529,6 @@ SurveyCell(struct nlist *tc, struct hashdict *compdict, int file1, int file2, in
if (dstr) *dstr = '[';
}
}
return retval;
}
/*------------------------------------------------------*/
@@ -1540,28 +1576,10 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
listX0 = list0X = NULL;
// Gather information about instances of cell "name1"
hascontents1 = SurveyCell(tc1, &compdict, file1, file2, 0);
SurveyCell(tc1, &compdict, file1, file2, 0);
// Gather information about instances of cell "name2"
hascontents2 = SurveyCell(tc2, &compdict, file1, file2, 1);
// If one cell has no contents, then flattening the other
// isn't going to improve anything, so stop here.
if (!hascontents1 && !hascontents2 && (tc1->flags & CELL_PLACEHOLDER)
&& (tc2->flags & CELL_PLACEHOLDER)) {
goto done;
}
else if (hascontents1 && !hascontents2 && (tc2->flags & CELL_PLACEHOLDER)) {
Fprintf(stdout, "Circuit 2 cell %s is a black box; will not flatten "
"Circuit 1\n", name2);
goto done;
}
else if (hascontents2 && !hascontents1 && (tc1->flags & CELL_PLACEHOLDER)) {
Fprintf(stdout, "Circuit 1 cell %s is a black box; will not flatten "
"Circuit 2\n", name1);
goto done;
}
SurveyCell(tc2, &compdict, file1, file2, 1);
// Find all instances of one cell that have fewer in
// the compared circuit. Check whether subcircuits
@@ -1611,19 +1629,22 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
}
}
if (match) {
if (ecomp->cell1 && (ecomp->num1 > 0)) {
Fprintf(stdout, "Flattening instances of %s in cell %s"
if (ecomp->cell1 && (ecomp->num1 > 0) &&
(!(ecomp->cell1->flags & CELL_PLACEHOLDER))) {
Fprintf(stdout, "Flattening instances of %s in cell %s (%d)"
" makes a better match\n", ecomp->cell1->name,
name1);
name1, file1);
flattenInstancesOf(name1, file1, ecomp->cell1->name);
modified++;
}
if (ecomp->cell2 && (ecomp->num2 > 0)) {
Fprintf(stdout, "Flattening instances of %s in cell %s"
if (ecomp->cell2 && (ecomp->num2 > 0) &&
(!(ecomp->cell2->flags & CELL_PLACEHOLDER))) {
Fprintf(stdout, "Flattening instances of %s in cell %s (%d)"
" makes a better match\n", ecomp->cell2->name,
name2);
name2, file2);
flattenInstancesOf(name2, file2, ecomp->cell2->name);
modified++;
}
modified++;
}
/* Reset or apply the count adjustments */
@@ -1700,13 +1721,21 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
}
}
if (match) {
if (ecomp->cell2) {
Fprintf(stdout, "Flattening instances of %s in cell %s"
/* Don't flatten if cell1 is a black box, because it */
/* can't also be flattened. */
if ((ecomp->num1 == 0) || (ecomp->cell1->class !=
CLASS_MODULE)) {
if (ecomp->cell2 && !(ecomp->cell2->flags & CELL_PLACEHOLDER)) {
Fprintf(stdout, "Flattening instances of %s in cell %s (%d)"
" makes a better match\n", ecomp->cell2->name,
name2);
flattenInstancesOf(name2, file2, ecomp->cell2->name);
name2, file2);
flattenInstancesOf(name2, file2, ecomp->cell2->name);
modified++;
}
}
modified++;
}
/* Reset or apply the count adjustments */
@@ -1730,7 +1759,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
}
/* Case 3: Cell1 class is a subcircuit, and flattening */
/* it (without regard to cell1) improves the matching. */
/* it (without regard to cell2) improves the matching. */
else if ((ecomp->num1 != ecomp->num2) && (ecomp->cell1 != NULL) &&
(ecomp->num1 != 0) && (ecomp->cell1->class == CLASS_SUBCKT)) {
@@ -1758,13 +1787,21 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
}
}
if (match) {
if (ecomp->cell1) {
Fprintf(stdout, "Flattening instances of %s in cell %s"
/* Don't flatten if cell2 is a black box, because it */
/* can't also be flattened. */
if ((ecomp->num2 == 0) || (ecomp->cell2->class !=
CLASS_MODULE)) {
if (ecomp->cell1 && !(ecomp->cell1->flags & CELL_PLACEHOLDER)) {
Fprintf(stdout, "Flattening instances of %s in cell %s (%d)"
" makes a better match\n", ecomp->cell1->name,
name1);
flattenInstancesOf(name1, file1, ecomp->cell1->name);
name1, file1);
flattenInstancesOf(name1, file1, ecomp->cell1->name);
modified++;
}
}
modified++;
}
/* Reset or apply the count adjustments */
@@ -1842,9 +1879,9 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
}
if (found) {
Fprintf(stdout, "Removing zero-valued device "
"%s from cell %s makes a better match\n",
tsub1->name,
tc1->name);
"%s from cell %s (%d) makes a better "
"match\n",
tsub1->name, tc1->name, tc1->file);
/* A current source is an open, while a */
/* resistor or voltage source is a short. */
@@ -1953,9 +1990,9 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
}
if (found) {
Fprintf(stdout, "Removing zero-valued device "
"%s from cell %s makes a better match\n",
tsub2->name,
tc2->name);
"%s from cell %s (%d) makes a better "
"match\n",
tsub2->name, tc2->name, tc2->file);
/* merge node of endpoints */
if (ecomp->cell2->class != CLASS_ISOURCE) {
@@ -2046,8 +2083,8 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
if (dstr) *dstr = '[';
if ((ncomp == ecomp0X) && (ecomp0X->num2 <= ecompX0->num1)) {
Fprintf(stdout, "Flattening instances of %s in cell %s"
" makes a better match\n", ecompX0->cell1->name,
name1);
"(%d) makes a better match\n",
ecompX0->cell1->name, name1, file1);
flattenInstancesOf(name1, file1, ecompX0->cell1->name);
ecompX0->num1 = 0;
ecomp0X->num1 += ecompX0->num1;
@@ -2072,8 +2109,8 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
if (dstr) *dstr = '[';
if ((ncomp == ecompX0) && (ecompX0->num1 <= ecomp0X->num2)) {
Fprintf(stdout, "Flattening instances of %s in cell %s"
" makes a better match\n", ecomp0X->cell2->name,
name2);
" (%d) makes a better match\n",
ecomp0X->cell2->name, name2, file2);
flattenInstancesOf(name2, file2, ecomp0X->cell2->name);
ecomp0X->num2 = 0;
ecompX0->num2 += ecomp0X->num2;
+1
View File
@@ -3,5 +3,6 @@
extern int UniquePins(char *name, int filenum);
extern void flattenCell(char *name, int file);
extern int HasContents(struct nlist *);
#endif /* _FLATTEN_H */
+252 -86
View File
@@ -875,7 +875,11 @@ struct FormattedList *FormatBadNodeFragment(struct Node *N)
for (n = pins[i]->subelement->element->nodelist; n != NULL; n = n->next){
if (n->pin_magic == pins[i]->subelement->pin_magic) {
if ((permute == 0) && (ob->instance.name != NULL)) {
pinname = ob->name + strlen(ob->instance.name) + 1;
/* Handle "port_match_error" */
if ((ob->name[0] == 'p') && !strcmp(ob->name, "port_match_error"))
pinname = ob->name;
else
pinname = ob->name + strlen(ob->instance.name) + 1;
}
else if (ob->instance.name != NULL) {
char *pinsave = pinname;
@@ -3122,6 +3126,47 @@ struct nlist *LookupPrematchedClass(struct nlist *tc1, int file2)
return tc2;
}
/*----------------------------------------------------------------------*/
/* Scan the property list of a device to find the number of devices */
/* implied by the total of M records. If the device does not have a */
/* property list, then return 1. If any property list does not have an */
/* "M" record, treat it as 1. */
/*----------------------------------------------------------------------*/
int GetNumDevices(struct objlist *ob)
{
int p, found, M = 0;
struct objlist *obs;
struct valuelist *vl;
obs = ob;
if (obs->type != PROPERTY)
for (obs = ob->next; obs && (obs->type != FIRSTPIN) &&
(obs->type != PROPERTY); obs = obs->next);
if ((obs == NULL) || (obs->type != PROPERTY)) return 1;
while (obs && (obs->type == PROPERTY)) {
found = FALSE;
for (p = 0; ; p++) {
vl = &obs->instance.props[p];
if (vl->type == PROP_ENDLIST) break;
if (vl->key == NULL) continue;
if ((*matchfunc)(vl->key, "M")) {
if (vl->type == PROP_DOUBLE)
M += (int)vl->value.dval;
else
M += vl->value.ival;
found = TRUE;
break;
}
}
if (found == FALSE) M++;
obs = obs->next;
}
return M;
}
/*----------------------------------------------------------------------*/
/* Attempt to define FirstElementPass that will generate element */
/* classes by names of pins, which will allow elements with different */
@@ -3143,7 +3188,7 @@ int FirstElementPass(struct Element *E, int noflat, int dolist)
struct Element *Esrch, *Ecorr;
struct NodeList *n;
struct nlist *tp1, *tp2, *tp;
int C1, C2, i;
int C1, C2, M1, M2, i;
char *ostr;
int needflat = 0;
#ifdef TCL_NETGEN
@@ -3184,6 +3229,8 @@ int FirstElementPass(struct Element *E, int noflat, int dolist)
Esrch->hashval = 1;
C1 = 1;
C2 = 0;
M2 = 0;
M1 = GetNumDevices(Esrch->object);
tp1 = LookupCellFile(Esrch->object->model.class, Circuit1->file);
tp2 = LookupClassEquivalent(Esrch->object->model.class, Circuit1->file,
Circuit2->file);
@@ -3195,6 +3242,7 @@ int FirstElementPass(struct Element *E, int noflat, int dolist)
if (tp && tp2 && (tp->classhash == tp2->classhash)) {
Ecorr->hashval = 1;
C2++;
M2 += GetNumDevices(Ecorr->object);
}
}
else if (Ecorr->graph == Circuit1->file) {
@@ -3203,6 +3251,7 @@ int FirstElementPass(struct Element *E, int noflat, int dolist)
if (tp && tp1 && (tp->classhash == tp1->classhash)) {
Ecorr->hashval = 1;
C1++;
M1 += GetNumDevices(Ecorr->object);
}
}
}
@@ -3219,10 +3268,19 @@ int FirstElementPass(struct Element *E, int noflat, int dolist)
for (i = 0; i < left_col_end; i++) *(ostr + i) = ' ';
for (i = left_col_end + 1; i < right_col_end; i++) *(ostr + i) = ' ';
snprintf(ostr, left_col_end, "%s (%d)", Esrch->object->model.class, C1);
if (C2 > 0)
snprintf(ostr + left_col_end + 1, left_col_end, "%s (%d)%s", tp2->name, C2,
(C2 == C1) ? "" : " **Mismatch**");
if (M1 == C1)
snprintf(ostr, left_col_end, "%s (%d)", Esrch->object->model.class, C1);
else
snprintf(ostr, left_col_end, "%s (%d->%d)", Esrch->object->model.class,
M1, C1);
if (C2 > 0) {
if (M2 == C2)
snprintf(ostr + left_col_end + 1, left_col_end, "%s (%d)%s", tp2->name,
C2, (C2 == C1) ? "" : " **Mismatch**");
else
snprintf(ostr + left_col_end + 1, left_col_end, "%s (%d->%d)%s",
tp2->name, M2, C2, (C2 == C1) ? "" : " **Mismatch**");
}
else {
snprintf(ostr + left_col_end + 1, left_col_end, "(no matching element)");
}
@@ -3261,6 +3319,7 @@ int FirstElementPass(struct Element *E, int noflat, int dolist)
if (Esrch->graph == Circuit2->file && Esrch->hashval == 0) {
Esrch->hashval = 1;
C2 = 1;
M2 = GetNumDevices(Esrch->object);
tp2 = LookupCellFile(Esrch->object->model.class, Circuit2->file);
tp1 = LookupClassEquivalent(Esrch->object->model.class, Circuit2->file,
Circuit1->file);
@@ -3272,6 +3331,7 @@ int FirstElementPass(struct Element *E, int noflat, int dolist)
if (tp->classhash == tp2->classhash) {
Ecorr->hashval = 1;
C2++;
M2 += GetNumDevices(Ecorr->object);
}
}
}
@@ -3287,7 +3347,12 @@ int FirstElementPass(struct Element *E, int noflat, int dolist)
for (i = 0; i < left_col_end; i++) *(ostr + i) = ' ';
for (i = left_col_end + 1; i < right_col_end; i++) *(ostr + i) = ' ';
snprintf(ostr, left_col_end, "(no matching element)");
snprintf(ostr + left_col_end + 1, left_col_end, "%s (%d)", Esrch->object->model.class, C2);
if (C2 == M2)
snprintf(ostr + left_col_end + 1, left_col_end, "%s (%d)",
Esrch->object->model.class, C2);
else
snprintf(ostr + left_col_end + 1, left_col_end, "%s (%d->%d)",
Esrch->object->model.class, M2, C2);
for (i = 0; i < right_col_end + 1; i++) if (*(ostr + i) == '\0') *(ostr + i) = ' ';
Fprintf(stdout, ostr);
}
@@ -3758,8 +3823,23 @@ void RemoveCompareQueue()
CompareQueue = NULL;
}
/*----------------------------------------------------------------------*/
/* Output a summary of the contents of the two circuits being compared */
/*----------------------------------------------------------------------*/
void DescribeContents(char *name1, int file1, char *name2, int file2)
{
Fprintf(stdout, "\n"); // blank line before new circuit diagnostics in log file
/* print preliminary statistics */
Printf("\nContents of circuit 1: ");
DescribeInstance(name1, file1);
Printf("Contents of circuit 2: ");
DescribeInstance(name2, file2);
Printf("\n");
}
/*----------------------------------*/
/* create an initial data structure */
/* Create an initial data structure */
/*----------------------------------*/
void CreateTwoLists(char *name1, int file1, char *name2, int file2, int dolist)
@@ -3771,14 +3851,6 @@ void CreateTwoLists(char *name1, int file1, char *name2, int file2, int dolist)
ResetState();
Fprintf(stdout, "\n"); // blank line before new circuit diagnostics in log file
/* print preliminary statistics */
Printf("\nContents of circuit 1: ");
DescribeInstance(name1, file1);
Printf("Contents of circuit 2: ");
DescribeInstance(name2, file2);
Printf("\n");
if (file1 == -1)
tc1 = LookupCell(name1);
else
@@ -4853,6 +4925,7 @@ int PropertyOptimize(struct objlist *ob, struct nlist *tp, int run, int series,
// Now combine records with same properties by summing M (S).
if (comb == FALSE) {
for (i = 0; i < run - 1; i++) {
int nr_empty = 0;
for (j = i + 1; j < run; j++) {
pmatch = 0;
for (p = 1; p < pcount; p++) {
@@ -4932,6 +5005,11 @@ int PropertyOptimize(struct objlist *ob, struct nlist *tp, int run, int series,
// find ith record in ob
p = 0;
for (ob2 = ob; p != i; ob2 = ob2->next, p++);
/* Sanity check */
if (ob2->type != PROPERTY) {
Fprintf(stderr, "Incorrect property run count!\n");
continue;
}
// Count entries, add one, reallocate
for (p = 0;; p++) {
vl = &ob2->instance.props[p];
@@ -4976,8 +5054,14 @@ int PropertyOptimize(struct objlist *ob, struct nlist *tp, int run, int series,
vlist[0][i]->value.ival += vlist[0][j]->value.ival;
vlist[0][j]->value.ival = 0;
}
else
nr_empty++;
}
}
// If everything from i to the end of the run has been matched
// and zeroed out, then nothing more can be merged.
if (nr_empty == (run - (i + 1)))
break;
}
}
@@ -6106,7 +6190,8 @@ void PrintPropertyResults(int do_list)
/*----------------------------------------------------------------------*/
/* Return 0 if perfect matching found, else return number of */
/* automorphisms, and return -1 if invalid matching found. */
/* automorphisms, and return -1 if invalid matching found, */
/* and return -2 if there is a port count mismatch. */
/*----------------------------------------------------------------------*/
int VerifyMatching(void)
@@ -6117,6 +6202,9 @@ int VerifyMatching(void)
struct Element *E;
struct Node *N;
int C1, C2, result;
int P1, P2;
struct objlist *ob1, *ob2;
int portMismatch = 0;
if (BadMatchDetected) return(-1);
@@ -6137,14 +6225,40 @@ int VerifyMatching(void)
}
}
P1 = P2 = 0;
for (NC = NodeClasses; NC != NULL; NC = NC->next) {
C1 = C2 = 0;
for (N = NC->nodes; N != NULL; N = N->next) {
(N->graph == Circuit1->file) ? C1++ : C2++;
if (IsPort(N->object)) (N->graph == Circuit1->file) ? P1++ : P2++;
}
if (C1 != C2) return(-1);
if (P1 != P2) portMismatch = 1;
if (C1 != 1) ret++;
}
P1 = P2 = 0;
if (ret == 0) { /* automorphisms have precedence over port count mismatch */
if (portMismatch) return -2;
/* Count ports in each subcircuit including disconnected ports */
for (ob1 = Circuit1->cell; ob1 && IsPort(ob1); ob1 = ob1->next, P1++);
for (ob2 = Circuit2->cell; ob2 && IsPort(ob2); ob2 = ob2->next, P2++);
if (P1 == P2) { // pin counts match. Make sure disconnected pins match, too.
for (ob1 = Circuit1->cell; ob1 && IsPort(ob1); ob1 = ob1->next) {
if (ob1->node == -1) { // disconnected pin
for (ob2 = Circuit2->cell; ob2 && IsPort(ob2); ob2 = ob2->next) {
if (ob2->node == -1 && (*matchfunc)(ob1->name, ob2->name))
break; // disconnected pin match
}
if (ob2 == NULL) return -2;
}
}
}
else { // pin count mismatch
return -2;
}
}
return(ret);
}
@@ -6243,7 +6357,7 @@ int ResolveAutomorphsByPin()
FractureElementClass(&ElementClasses);
FractureNodeClass(&NodeClasses);
ExhaustiveSubdivision = 1;
while (!Iterate() && VerifyMatching() != -1);
while (!Iterate() && VerifyMatching() >= 0);
return(VerifyMatching());
}
@@ -6346,7 +6460,7 @@ int ResolveAutomorphsByProperty()
FractureElementClass(&ElementClasses);
FractureNodeClass(&NodeClasses);
ExhaustiveSubdivision = 1;
while (!Iterate() && VerifyMatching() != -1);
while (!Iterate() && VerifyMatching() >= 0);
return(VerifyMatching());
}
@@ -6423,7 +6537,7 @@ int ResolveAutomorphisms()
FractureElementClass(&ElementClasses);
FractureNodeClass(&NodeClasses);
ExhaustiveSubdivision = 1;
while (!Iterate() && VerifyMatching() != -1);
while (!Iterate() && VerifyMatching() >= 0);
return(VerifyMatching());
}
@@ -7118,37 +7232,36 @@ struct nlist *addproxies(struct hashlist *p, void *clientdata)
return NULL; /* Keep the search going */
}
/*------------------------------------------------------*/
/* Declare that the device class "name1" is equivalent */
/* to class "name2". This is the same as the above */
/* routine, except that the cells must be at the top */
/* of the compare queue, and must already be proven */
/* equivalent by LVS. Determine a pin correspondence, */
/* then modify all instances of "name2" to match all */
/* instances of "name1" by pin reordering. If either */
/* cell has disconnected pins, they are shuffled to the */
/* end of the pin list. If two or more pins correspond */
/* to net automorphisms, then they are added to the */
/* list of permuted pins. */
/* */
/* NOTE: This routine must not be called on any */
/* circuit pair that has not been matched. If a */
/* circuit pair has been matched with automorphisms, */
/* then some pins may be matched arbitrarily. */
/* */
/* If "dolist" is 1, append the list representing the */
/* output (if any) to variable tcl_out, if it exists. */
/* */
/* Return codes: */
/* 2: Neither cell had pins, so matching is unnecessary */
/* 1: Exact match */
/* 0: Inexact match resolved by proxy pin insertion */
/*------------------------------------------------------*/
/*--------------------------------------------------------------*/
/* Declare that the device class "name1" is equivalent to class */
/* "name2". This is the same as the above routine, except that */
/* the cells must be at the top of the compare queue, and must */
/* already be proven equivalent by LVS. Determine a pin */
/* correspondence, then modify all instances of "name2" to */
/* match all instances of "name1" by pin reordering. If either */
/* cell has disconnected pins, they are shuffled to the end of */
/* the pin list. If two or more pins correspond to net */
/* automorphisms, then they are added to the list of permuted */
/* pins. */
/* */
/* NOTE: This routine must not be called on any circuit pair */
/* that has not been matched. If a circuit pair has been */
/* matched with automorphisms, then some pins may be matched */
/* arbitrarily. */
/* */
/* If "dolist" is 1, append the list representing the output */
/* (if any) to variable tcl_out, if it exists. */
/* */
/* Return codes: */
/* 2: Neither cell had pins, so matching is unnecessary */
/* 1: Exact match */
/* 0: Inexact match resolved by proxy pin insertion. */
/*--------------------------------------------------------------*/
int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
{
char *cover, *ctemp;
char *bangptr1, *bangptr2;
char *bangptr1, *bangptr2, *backslashptr1, *backslashptr2;
struct objlist *ob1, *ob2, *obn, *obp, *ob1s, *ob2s, *obt;
struct NodeClass *NC;
struct Node *N1, *N2;
@@ -7222,8 +7335,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
if (IsPort(obn)) {
i = 0;
for (ob1 = tc1->cell; ob1 != NULL; ob1 = ob1->next, i++) {
if ((IsPort(ob1))
&& (*matchfunc)(ob1->name, obn->name)) {
if ((IsPort(ob1)) && (ob1->node == obn->node)) {
b = 0;
for (N2 = NC->nodes; N2 != NULL; N2 = N2->next) {
if (N2->graph != Circuit1->file) {
@@ -7248,20 +7360,41 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
obp = N2->object;
j = 0;
for (ob2 = tc2->cell; ob2 != NULL; ob2 = ob2->next, j++) {
if ((IsPort(ob2))
&& (*matchfunc)(ob2->name, obp->name)) {
if ((IsPort(ob2)) && (ob2->node == obp->node)) {
if (Debug == 0) {
for (m = 0; m < left_col_end; m++) *(ostr + m) = ' ';
for (m = left_col_end + 1; m < right_col_end; m++) *(ostr + m) = ' ';
snprintf(ostr, left_col_end, "%s", obn->name);
if ((*matchfunc)(obn->name, obp->name))
snprintf(ostr + left_col_end + 1, left_col_end, "%s", obp->name);
snprintf(ostr, left_col_end, "%s", ob1->name);
if ((*matchfunc)(ob1->name, ob2->name))
snprintf(ostr + left_col_end + 1, left_col_end, "%s", ob2->name);
else {
snprintf(ostr + left_col_end + 1, left_col_end, "%s **Mismatch**", obp->name);
/* Pins with different names are on different nets,
* so this should trigger an error return code.
/* Check remainder of ports to see if there is a name match on the
* same net number (multiple ports tied to the same net)
*/
result = 0;
struct objlist *ob3;
for (ob3 = ob2->next, ++j; ob3 != NULL; ob3 = ob3->next, j++) {
if ((IsPort(ob3)) && (ob3->node == ob2->node)) {
if ((*matchfunc)(ob3->name, ob1->name)) {
ob2 = ob3;
snprintf(ostr + left_col_end + 1, left_col_end, "%s", ob2->name);
break;
}
}
else {
ob3 = NULL;
break; /* All pins w/the same node should be together */
}
}
if (ob3 == NULL) {
if (ob2->model.port == -1)
snprintf(ostr + left_col_end + 1, left_col_end, "%s **Mismatch**", ob2->name);
else
snprintf(ostr + left_col_end + 1, left_col_end, "(no matching pin)");
/* Pins with different names are on different nets,
* so this should trigger an error return code.
*/
result = 0;
}
}
for (m = 0; m < right_col_end + 1; m++)
if (*(ostr + m) == '\0') *(ostr + m) = ' ';
@@ -7283,7 +7416,16 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
#endif
ob2->model.port = i; /* save order */
*(cover + i) = (char)1;
break;
/* If there are multiple pins on the same net, cycle through them; */
/* otherwise, move to the next entry in the partition. */
if (ob1->next && (ob1->next->type == PORT) && (ob1->next->node == ob1->node)) {
ob1 = ob1->next;
ob2 = tc2->cell; /* Restart search for matching pin */
i++;
}
else
break;
}
}
if (ob2 == NULL) {
@@ -7374,14 +7516,21 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
/* This should not happen if unconnected pins are eliminated */
/* so apply only to black-box (CELL_PLACEHOLDER) entries. */
/* (Semi-hack: Allow "!" global flag) */
/* (Another semi-hack: Ignore the leading backslash in */
/* backslash-escaped verilog names. Removing the backslash */
/* and ending space character is a common way to convert to */
/* legal SPICE. */
ob1 = tc1->cell;
bangptr1 = strrchr(ob1->name, '!');
if (bangptr1 && (*(bangptr1 + 1) == '\0'))
*bangptr1 = '\0';
else bangptr1 = NULL;
for (i = 0; i < numorig; i++) {
bangptr1 = strrchr(ob1->name, '!');
if (bangptr1 && (*(bangptr1 + 1) == '\0'))
*bangptr1 = '\0';
else bangptr1 = NULL;
backslashptr1 = (*(ob1->name) == '\\') ? ob1->name + 1 : ob1->name;
if (*(cover + i) == (char)0) {
j = 0;
for (ob2 = tc2->cell; ob2 != NULL; ob2 = ob2->next) {
@@ -7394,8 +7543,10 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
*bangptr2 = '\0';
else bangptr2 = NULL;
name1 = ob1->name;
name2 = ob2->name;
backslashptr2 = (*(ob2->name) == '\\') ? ob2->name + 1 : ob2->name;
name1 = backslashptr1;
name2 = backslashptr2;
/* Recognize proxy pins as matching unconnected pins */
if (!strncmp(name1, "proxy", 5) && (ob2->node == -1)) name1 +=5;
@@ -7700,7 +7851,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
}
/* Check for ports that did not get ordered */
for (obn = tc2->cell; obn && (obn->type == PORT); obn = obn->next) {
for (obn = tc2->cell; obn && IsPort(obn); obn = obn->next) {
if (obn->model.port == -1) {
if (obn->node == -1) {
// This only happens when pins have become separated from any net.
@@ -7878,10 +8029,12 @@ int EquivalentElement(char *name, struct nlist *circuit, struct objlist **retobj
void FlattenCurrent()
{
if (Circuit1 != NULL && Circuit2 != NULL) {
Fprintf(stdout, "Flattening subcell %s\n", Circuit1->name);
Fprintf(stdout, "Flattening subcell %s (%d)\n", Circuit1->name,
Circuit1->file);
FlattenInstancesOf(Circuit1->name, Circuit1->file);
Fprintf(stdout, "Flattening subcell %s\n", Circuit2->name);
Fprintf(stdout, "Flattening subcell %s (%d)\n", Circuit2->name,
Circuit2->file);
FlattenInstancesOf(Circuit2->name, Circuit2->file);
}
}
@@ -7938,6 +8091,7 @@ int Compare(char *cell1, char *cell2)
{
int automorphisms;
DescribeContents(cell1, -1, cell2, -1);
CreateTwoLists(cell1, -1, cell2, -1, 0);
Permute();
while (!Iterate());
@@ -7951,7 +8105,25 @@ int Compare(char *cell1, char *cell2)
PrintIllegalClasses();
return(0);
}
if (automorphisms == 0) Fprintf(stdout, "Circuits match correctly.\n");
if (automorphisms > 0) {
Fprintf(stdout, "Circuits match with %d symmetries.\n", automorphisms);
if (VerboseOutput) PrintAutomorphisms();
/* arbitrarily resolve automorphisms */
Fprintf(stdout, "\n");
Fprintf(stdout, "Resolving automorphisms by arbitrary symmetry breaking:\n");
while ((automorphisms = ResolveAutomorphisms()) > 0) ;
if (automorphisms == -1) {
MatchFail(cell1, cell2);
Fprintf(stdout, "Circuits do not match.\n");
return 0;
}
}
if (automorphisms == -2) { // Port count mismatch
Fprintf(stderr, "Port counts do not match.\n");
return 0;
}
if (PropertyErrorDetected == 1) {
Fprintf(stdout, "There were property errors.\n");
PrintPropertyResults(0);
@@ -7960,22 +8132,10 @@ int Compare(char *cell1, char *cell2)
Fprintf(stdout, "There were missing properties.\n");
PrintPropertyResults(0);
}
if (automorphisms == 0) return(1);
else
Fprintf(stdout, "Circuits match correctly.\n");
Fprintf(stdout, "Circuits match with %d automorphisms.\n", automorphisms);
if (VerboseOutput) PrintAutomorphisms();
/* arbitrarily resolve automorphisms */
Fprintf(stdout, "\n");
Fprintf(stdout, "Resolving automorphisms by arbitrary symmetry breaking:\n");
while ((automorphisms = ResolveAutomorphisms()) > 0) ;
if (automorphisms == -1) {
MatchFail(cell1, cell2);
Fprintf(stdout, "Circuits do not match.\n");
return(0);
}
Fprintf(stdout, "Circuits match correctly.\n");
return(1);
return 1;
}
@@ -7998,6 +8158,7 @@ void NETCOMP(void)
case 'c':
promptstring("Enter cell 1: ",name);
promptstring("Enter cell 2: ",name2);
DescribeContents(name, -1, name2, -1);
CreateTwoLists(name, -1, name2, -1, 0);
#ifdef DEBUG_ALLOC
PrintCoreStats();
@@ -8028,9 +8189,12 @@ void NETCOMP(void)
PrintIllegalClasses();
Fprintf(stdout, "Netlists do not match.\n");
}
else if (automorphisms == -2) { // port count mismatch
Fprintf(stdout, "Port counts do not match.\n");
}
else {
if (automorphisms)
Printf("Circuits match with %d automorphisms.\n", automorphisms);
Printf("Circuits match with %d symmetries.\n", automorphisms);
else Printf("Circuits match correctly.\n");
}
}
@@ -8043,11 +8207,13 @@ void NETCOMP(void)
while (!Iterate()) ;
automorphisms = VerifyMatching();
if (automorphisms == -1) Fprintf(stdout, "Netlists do not match.\n");
else if (automorphisms == -2) Fprintf(stdout, "Port counts do not match.\n");
else {
Printf("Netlists match with %d automorphisms.\n", automorphisms);
Printf("Netlists match with %d symmetries.\n", automorphisms);
while ((automorphisms = ResolveAutomorphisms()) > 0)
Printf(" automorphisms = %d.\n", automorphisms);
if (automorphisms == -1) Fprintf(stdout, "Netlists do not match.\n");
else if (automorphisms == -2) Fprintf(stdout, "Port counts do not match.\n");
else Printf("Circuits match correctly.\n");
}
}
+2
View File
@@ -26,6 +26,7 @@ extern void PrintCoreStats(void);
extern void ResetState(void);
extern void CreateTwoLists(char *name1, int file1, char *name2, int file2,
int dolist);
extern void DescribeContents(char *name1, int file1, char *name2, int file2);
extern int Iterate(void);
extern int VerifyMatching(void);
extern void PrintAutomorphisms(void);
@@ -46,6 +47,7 @@ extern int CreateCompareQueue(char *, int, char *, int);
extern int GetCompareQueueTop(char **, int *, char **, int *);
extern int PeekCompareQueueTop(char **, int *, char **, int *);
extern void RemoveCompareQueue();
extern int FlattenUnmatched(struct nlist *, char *, int, int);
extern void PrintIllegalClasses();
extern void PrintIllegalNodeClasses();
+73 -63
View File
@@ -331,77 +331,87 @@ int GetNextLineNoNewline(char *delimiter)
linetok = (char *)MALLOC(linesize + 1);
}
/* Check for substitutions (verilog only). Make sure linetok is */
/* large enough to hold the entire line after substitutions. */
if (definitions != NULL) {
char *s, *w, e;
struct property *kl;
int len, dlen, vlen, addin = 0;
unsigned char found = FALSE;
for (s = line; *s != '\0'; s++) {
if (*s == '`') {
w = s + 1;
while (isalnum(*w) || (*w == '_') || (*w == '$')) w++;
e = *w;
*w = '\0';
kl = (struct property *)HashLookup(s + 1, definitions);
if (kl != NULL) {
dlen = strlen(s);
if (kl->type == PROP_STRING) {
vlen = strlen(kl->pdefault.string);
}
else vlen = 12; /* Leave room for numeric conversion */
addin += vlen - dlen + 1;
found = TRUE;
}
*w = e;
}
}
if (found) {
len = strlen(line);
if (len + addin > linesize) {
while (len + addin > linesize) linesize += 500;
FREE(linetok);
linetok = (char *)MALLOC(linesize);
}
}
}
/* Make definition substitutions (verilog only) */
if (definitions != NULL) {
if (definitions == NULL)
strcpy(linetok, line);
else {
char *s, *t, *w, e;
struct property *kl;
int len, dlen, vlen, addin = 0;
int oldlinesize = linesize;
unsigned char found = TRUE;
t = linetok;
for (s = line; *s != '\0'; s++) {
if (*s == '`') {
w = s + 1;
while (isalnum(*w) || (*w == '_') || (*w == '$')) w++;
e = *w;
*w = '\0';
kl = (struct property *)HashLookup(s + 1, definitions);
if (kl != NULL) {
if (kl->type == PROP_STRING)
strcpy(t, kl->pdefault.string);
else if (kl->type == PROP_INTEGER)
sprintf(t, "%d", kl->pdefault.ival);
else if (kl->type == PROP_DOUBLE)
sprintf(t, "%g", kl->pdefault.dval);
t += strlen(t);
s = w - 1;
/* Check for substitutions (verilog only). Make sure linetok is */
/* large enough to hold the entire line after substitutions. */
while (found) { /* Do this recursively, for nested definitions */
found = FALSE;
for (s = line; *s != '\0'; s++) {
if (*s == '`') {
w = s + 1;
while (isalnum(*w) || (*w == '_') || (*w == '$')) w++;
e = *w;
*w = '\0';
kl = (struct property *)HashLookup(s + 1, definitions);
if (kl != NULL) {
dlen = strlen(s);
if (kl->type == PROP_STRING) {
vlen = strlen(kl->pdefault.string);
}
else vlen = 12; /* Leave room for numeric conversion */
addin += vlen - dlen + 1;
found = TRUE;
}
*w = e;
}
}
if (found) {
len = strlen(line);
if (len + addin > linesize) {
while (len + addin > linesize) linesize += 500;
FREE(linetok);
linetok = (char *)MALLOC(linesize);
}
}
/* Make definition substitutions (verilog only) */
t = linetok;
for (s = line; *s != '\0'; s++) {
if (*s == '`') {
w = s + 1;
while (isalnum(*w) || (*w == '_') || (*w == '$')) w++;
e = *w;
*w = '\0';
kl = (struct property *)HashLookup(s + 1, definitions);
if (kl != NULL) {
if (kl->type == PROP_STRING)
strcpy(t, kl->pdefault.string);
else if (kl->type == PROP_INTEGER)
sprintf(t, "%d", kl->pdefault.ival);
else if (kl->type == PROP_DOUBLE)
sprintf(t, "%g", kl->pdefault.dval);
t += strlen(t);
s = w - 1;
}
else *t++ = *s;
*w = e;
}
else *t++ = *s;
*w = e;
}
*t = '\0';
/* Copy substituted linetok back to line and repeat until */
/* there are no more substitutions to be made. */
if (oldlinesize != linesize) {
FREE(line);
line = (char *)MALLOC(linesize + 501);
oldlinesize = linesize;
}
else *t++ = *s;
strcpy(line, linetok);
}
*t = '\0';
}
else
strcpy(linetok, line);
TrimQuoted(linetok);
linenum++;
+24 -26
View File
@@ -3337,16 +3337,13 @@ int CombineParallel(char *model, int file)
/* "sob" to it. If "ob" does not have properties, then */
/* create a property record and set property "M" to 1. */
/* Find last non-property record of sob ( = pob) */
/* Find first property record of sob ( = spropfirst) */
/* Find last property record of sob ( = sproplast) */
/* Find last non-property record of sob ( = pob) */
/* Find first property record of sob ( = spropfirst) */
spropfirst = sproplast = NULL;
spropfirst = NULL;
for (ob2 = sob; ob2->type > FIRSTPIN || ob2 == sob; ob2 = ob2->next)
pob = ob2;
if (ob2->type == PROPERTY) spropfirst = ob2;
for (; ob2->type == PROPERTY; ob2 = ob2->next)
sproplast = ob2;
if (spropfirst == NULL) {
/* Create new property instance record if one doesn't exist */
@@ -3372,8 +3369,9 @@ int CombineParallel(char *model, int file)
nob->next = pob->next;
pob->next = nob;
/* Handle case of contiguous entries */
if (lob == pob) lob = nob;
spropfirst = sproplast = nob;
spropfirst = nob;
}
if (propfirst == NULL) {
/* Create new property instance record if one doesn't exist */
@@ -3396,27 +3394,26 @@ int CombineParallel(char *model, int file)
kv->type = PROP_ENDLIST;
kv->value.ival = 0;
/* Append to sob's property list */
nob->next = sproplast->next;
sproplast->next = nob;
if (lob == sproplast) lob = nob;
/* Prepend to sob's property list */
nob->next = pob->next;
pob->next = nob;
/* Handle case of contiguous entries */
if (lob == pob) lob = nob;
}
if (propfirst != NULL) {
else {
// Series/Parallel logic:
// If propfirst has _tag in properties,
// then add an "open" tag at propfirst
add_prop_tag(propfirst, '(');
// If spropfirst has _tag in properties,
// then add an "open" tag at spropfirst
add_prop_tag(spropfirst, '(');
// if spropfirst has _tag in properties then add an "open" tag
// to spropfirst and a "close" tag to propfirst
if (add_prop_tag(spropfirst, '(')) add_prop_tag(propfirst, ')');
// if propfirst has _tag in properties then add an "open" tag
// to propfirst and a "close" tag to spropfirst
if (add_prop_tag(propfirst, '(')) add_prop_tag(spropfirst, ')');
/* Append ob's property list to sob */
proplast->next = sproplast->next;
sproplast->next = propfirst;
if (lob == sproplast) lob = proplast;
/* Prepend ob's property list to sob */
proplast->next = pob->next;
pob->next = propfirst;
}
/* Link up around object to be removed */
@@ -3429,7 +3426,6 @@ int CombineParallel(char *model, int file)
obr = nob;
}
dcnt++;
}
FREE((char *)pstr);
}
@@ -3441,7 +3437,8 @@ int CombineParallel(char *model, int file)
}
HashKill(&devdict);
if (dcnt > 0) {
Fprintf(stdout, "Class %s(%d): Merged %d parallel devices.\n", model, file, dcnt);
Fprintf(stdout, "Class %s (%d): Merged %d parallel devices.\n",
model, file, dcnt);
}
FREE(nodecount);
return dcnt;
@@ -3739,7 +3736,8 @@ int CombineSeries(char *model, int file)
}
FREE(instlist);
if (scnt > 0) {
Fprintf(stdout, "Class %s(%d): Merged %d series devices.\n", model, file, scnt);
Fprintf(stdout, "Class %s (%d): Merged %d series devices.\n",
model, file, scnt);
}
return scnt;
}
+7 -4
View File
@@ -805,11 +805,14 @@ void DescribeInstance(char *name, int file)
/* All black-box modules and placeholders by definition have all */
/* disconnected pins, so don't report those. */
if (!(tp->flags & CELL_PLACEHOLDER) && (tp->class != CLASS_MODULE))
{
//if (disconnectednodes == 0) Fprintf(stderr, "\n");
if ((!(tp->flags & CELL_PLACEHOLDER)) && (tp->class != CLASS_MODULE)) {
// if (disconnectednodes == 0) Fprintf(stderr, "\n");
disconnectednodes++;
Fprintf(stderr, "Cell %s(%d) disconnected node: %s\n", tp->name, tp->file, ob->name);
/* Don't report on ports marked "port_match_error", which is just confusing. */
if (strcmp(ob->name, "port_match_error")) {
Fprintf(stderr, "Cell %s (%d) disconnected node: %s\n",
tp->name, tp->file, ob->name);
}
}
}
}
+23 -10
View File
@@ -940,7 +940,7 @@ skip_ends:
goto baddevice;
}
snprintf(instname, 255, "%s%s", model, inst);
snprintf(instname, 255, "%s:%s", model, inst);
Cell(instname, model, collector, base, emitter);
pobj = LinkProperties(model, kvlist);
ReduceExpressions(pobj, NULL, CurrentCell, TRUE);
@@ -1013,7 +1013,7 @@ skip_ends:
goto baddevice;
}
snprintf(instname, 255, "%s%s", model, inst);
snprintf(instname, 255, "%s:%s", model, inst);
Cell(instname, model, drain, gate, source, bulk);
pobj = LinkProperties(model, kvlist);
ReduceExpressions(pobj, NULL, CurrentCell, TRUE);
@@ -1104,7 +1104,7 @@ skip_ends:
usemodel = 1;
}
snprintf(instname, 255, "%s%s", model, inst);
snprintf(instname, 255, "%s:%s", model, inst);
if (usemodel)
Cell(instname, model, ctop, cbot);
else
@@ -1197,7 +1197,7 @@ skip_ends:
else
strcpy(model, "r"); /* Use default resistor model */
snprintf(instname, 255, "%s%s", model, inst);
snprintf(instname, 255, "%s:%s", model, inst);
if (usemodel)
Cell(instname, model, rtop, rbot);
else
@@ -1255,7 +1255,7 @@ skip_ends:
Fprintf(stderr, "Device \"%s\" has wrong number of ports for a diode.\n");
goto baddevice;
}
snprintf(instname, 255, "%s%s", model, inst);
snprintf(instname, 255, "%s:%s", model, inst);
Cell(instname, model, anode, cathode);
pobj = LinkProperties(model, kvlist);
ReduceExpressions(pobj, NULL, CurrentCell, TRUE);
@@ -1334,7 +1334,7 @@ skip_ends:
else
strcpy(model, "t"); /* Use default xline model */
snprintf(instname, 255, "%s%s", model, inst);
snprintf(instname, 255, "%s:%s", model, inst);
if (usemodel)
Cell(instname, model, node1, node2, node3, node4);
@@ -1417,7 +1417,7 @@ skip_ends:
else
strcpy(model, "l"); /* Use default inductor model */
snprintf(instname, 255, "%s%s", model, inst);
snprintf(instname, 255, "%s:%s", model, inst);
if (usemodel)
Cell(instname, model, end_a, end_b);
else
@@ -1449,7 +1449,20 @@ skip_ends:
if (LookupObject(pos, CurrentCell) == NULL) Node(pos);
if (LookupObject(neg, CurrentCell) == NULL) Node(neg);
/* Any device properties? */
/* Get voltage value (if present); save as property "value" */
if (nexttok != NULL) {
if (matchnocase(nexttok, "DC")) {
SpiceTokNoNewline();
}
}
if (nexttok != NULL) {
if (StringIsValueOrExpression(nexttok)) {
AddProperty(&kvlist, "value", nexttok);
}
}
/* Any other device properties? */
while (nexttok != NULL)
{
SpiceTokNoNewline();
@@ -1477,7 +1490,7 @@ skip_ends:
else if (CountPorts(model, filenum) != 2) {
/* Modeled device: Make sure it has the right number of ports */
Fprintf(stderr, "Device \"%s\" has wrong number of ports for a "
"voltage source.\n");
"voltage source.\n", inst);
goto baddevice;
}
Cell(instname, model, pos, neg);
@@ -1729,7 +1742,7 @@ skip_ends:
/* names. */
if (strncmp(instancename, scan->name, strlen(scan->name))) {
snprintf(subcktname, 99, "%s%s", scan->name, instancename);
snprintf(subcktname, 99, "%s:%s", scan->name, instancename);
strcpy(instancename, subcktname);
}
else {
+306 -170
View File
@@ -60,6 +60,7 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
// See netfile.c for explanation of delimiters. 'X'
// separates single-character delimiters from two-character delimiters.
#define VLOG_DELIMITERS "X///**/#((**)X,;:(){}[]="
#define VLOG_EQUATION_DELIMITERS "X///**/#((**)X,;:(){}[]=+-*/"
#define VLOG_PIN_NAME_DELIMITERS "X///**/(**)X()"
#define VLOG_PIN_CHECK_DELIMITERS "X///**/(**)X,;(){}"
@@ -71,6 +72,8 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
struct hashdict verilogparams;
// Global storage for verilog definitions
struct hashdict verilogdefs;
// Record file pointer that is associated with the hash tables
int hashfile = -1;
// Global storage for wire buses
struct hashdict buses;
@@ -127,6 +130,187 @@ char *strvchr(char *string, char c)
return NULL;
}
/* Linked list, much like tokstack in netgen.c, but much simpler. */
/* contents are either a value, if oper = 0, or an operator. */
struct expr_stack {
int value;
char oper;
struct expr_stack *next;
struct expr_stack *last;
};
//-------------------------------------------------------------------------
// Evaluate an expression for an array bound. This is much like
// ReduceOneExpression() in netgen.c, but only handles basic integer
// arithmetic (+,-,*,/) and grouping by parentheses.
//
// Returns 1 if successful, 0 on error.
// Evaluated result is placed in the integer pointed to by "valptr".
//-------------------------------------------------------------------------
int EvalExpr(struct expr_stack **stackptr, int *valptr)
{
struct expr_stack *texp, *start, *tmp, *stack;
int modified, value;
stack = *stackptr;
/* Most expressions are going to be just one number, so treat
* that as a special case.
*/
if ((stack->oper == '\0') && (stack->last == NULL)) {
*valptr = stack->value;
FREE(stack);
*stackptr = NULL;
return 1;
}
/* Move to the end of the stack, which is the beginning of the
* expression.
*/
for (start = stack; start->last; start = start->last);
/* Run passes until no more modifications can be made */
modified = TRUE;
while (modified == TRUE) {
modified = FALSE;
/* Find any + or - that is used as a sign of a value */
for (texp = start; texp; texp = texp->next) {
if ((texp->oper == '+') || (texp->oper == '-') || (texp->oper == '*') ||
(texp->oper == '/') || (texp->oper == '(')) {
if ((texp->next != NULL) && (texp->next->next != NULL) &&
(texp->next->next->oper == '\0')) {
if (texp->next->oper == '+') {
/* Remove the unnecessary sign */
tmp = texp->next;
texp->next = tmp->next;
tmp->next->last = texp;
FREE(tmp);
modified = TRUE;
}
else if (texp->next->oper == '-') {
/* Remove the sign and negate the value */
tmp = texp->next;
texp->next->next->value = -texp->next->next->value;
texp->next = tmp->next;
tmp->next->last = texp;
FREE(tmp);
modified = TRUE;
}
}
}
}
/* Reduce (a * b) and (a / b) */
for (texp = start; texp; texp = texp->next) {
if ((texp->last != NULL) && (texp->next != NULL) && (texp->oper != '\0')) {
if ((texp->last->oper == '\0') && (texp->next->oper == '\0')) {
if (texp->oper == '*') {
/* Multiply */
texp->last->value *= texp->next->value;
/* Remove two items from the stack */
tmp = texp;
texp = texp->last;
texp->next = tmp->next->next;
if (tmp->next->next) tmp->next->next->last = texp;
FREE(tmp->next);
FREE(tmp);
modified = TRUE;
}
if (texp->oper == '/') {
/* Divide */
texp->last->value /= texp->next->value;
/* Remove two items from the stack */
tmp = texp;
texp = texp->last;
texp->next = tmp->next->next;
if (tmp->next->next) tmp->next->next->last = texp;
FREE(tmp->next);
FREE(tmp);
modified = TRUE;
}
}
}
}
/* Reduce (a + b) and (a - b) */
for (texp = start; texp; texp = texp->next) {
if ((texp->last != NULL) && (texp->next != NULL) && (texp->oper != '\0')) {
if ((texp->last->oper == '\0') && (texp->next->oper == '\0')) {
if (texp->oper == '-') {
/* Subtract */
texp->last->value -= texp->next->value;
/* Remove two items from the stack */
tmp = texp;
texp = texp->last;
texp->next = tmp->next->next;
if (tmp->next->next) tmp->next->next->last = texp;
FREE(tmp->next);
FREE(tmp);
modified = TRUE;
}
if (texp->oper == '+') {
/* Add */
texp->last->value += texp->next->value;
/* Remove two items from the stack */
tmp = texp;
texp = texp->last;
texp->next = tmp->next->next;
if (tmp->next->next) tmp->next->next->last = texp;
FREE(tmp->next);
FREE(tmp);
modified = TRUE;
}
}
}
}
/* Reduce (a) */
for (texp = start; texp; texp = texp->next) {
if ((texp->last != NULL) && (texp->next != NULL) && (texp->oper == '\0')) {
if ((texp->last->oper == '(') && (texp->next->oper == ')')) {
tmp = texp->last;
texp->last->oper = '\0';
texp->last->value = texp->value;
texp->last->next = texp->next->next;
if (texp->next->next) texp->next->next->last = texp->last;
FREE(texp->next);
FREE(texp);
texp = tmp;
modified = TRUE;
}
}
}
}
/* If only one numerical item remains, then place it in valptr and return 1 */
texp = start;
if ((texp->oper == '\0') && (texp->next == NULL)) {
*valptr = texp->value;
FREE(texp);
*stackptr = NULL;
return 1;
}
/* Clean up the stack before returning error status */
while (texp) {
tmp = texp;
texp = texp->next;
FREE(tmp);
}
*stackptr = NULL;
return 0;
}
//-------------------------------------------------------------------------
// Get bus indexes from the notation name[a:b]. If there is only "name"
// then look up the name in the bus hash list and return the index bounds.
@@ -138,147 +322,123 @@ char *strvchr(char *string, char c)
int GetBusTok(struct bus *wb)
{
int result, start, end;
int result, start, end, value;
char oper;
struct property *kl = NULL;
struct expr_stack *stack, *newexp;
if (wb == NULL) return 0;
else {
wb->start = -1;
wb->end = -1;
}
wb->start = -1;
wb->end = -1;
stack = NULL;
/* Parse a value for array bounds [a : b], including possible use */
/* of parameters, definitions, and basic arithmetic. */
if (match(nexttok, "[")) {
SkipTokComments(VLOG_DELIMITERS);
result = sscanf(nexttok, "%d", &start);
if (result != 1) {
char *aptr = NULL;
char addin;
// Check for "+/-(n)" at end of a parameter name
aptr = strrchr(nexttok, '+');
if (aptr == NULL) aptr = strrchr(nexttok, '-');
if (aptr != NULL) {
addin = *aptr;
*aptr = '\0';
}
// Is name in the parameter list?
kl = (struct property *)HashLookup(nexttok, &verilogparams);
if (kl == NULL) {
Printf("Array value %s is not a number or a parameter.\n",
nexttok);
return 1;
}
else {
if (kl->type == PROP_STRING) {
result = sscanf(kl->pdefault.string, "%d", &start);
if (result != 1) {
Printf("Parameter %s has value %s that cannot be parsed"
" as an integer.\n", nexttok, kl->pdefault.string);
return 1;
}
}
else if (kl->type == PROP_INTEGER) {
start = kl->pdefault.ival;
}
else if (kl->type == PROP_DOUBLE) {
start = (int)kl->pdefault.dval;
if ((double)start != kl->pdefault.dval) {
Printf("Parameter %s has value %g that cannot be parsed"
" as an integer.\n", nexttok, kl->pdefault.dval);
return 1;
}
}
else {
Printf("Parameter %s has unknown type; don't know how"
" to parse.\n", nexttok);
start = end = -1;
oper = '\0';
while (nexttok) {
SkipTokComments(VLOG_EQUATION_DELIMITERS);
if (match(nexttok, "]")) {
result = 1;
if (stack == NULL) {
Printf("Empty array found.\n");
return 1;
}
}
if (aptr != NULL) {
int addval;
*aptr = addin;
if (sscanf(aptr + 1, "%d", &addval) != 1) {
Printf("Unable to parse parameter increment '%s'\n", aptr);
if (EvalExpr(&stack, &end) != 1) {
Printf("Bad expression found in array.\n");
return 1;
}
start += (addin == '+') ? addval : -addval;
if (start == -1) start = end; // Single bit
break;
}
}
SkipTokComments(VLOG_DELIMITERS);
if (match(nexttok, "]")) {
result = 1;
end = start; // Single bit
}
else if (!match(nexttok, ":")) {
Printf("Badly formed array notation: Expected colon, found %s\n", nexttok);
return 1;
}
else {
SkipTokComments(VLOG_DELIMITERS);
result = sscanf(nexttok, "%d", &end);
if (result != 1) {
char *aptr = NULL;
char addin;
// Check for "+/-(n)" at end of a parameter name
aptr = strrchr(nexttok, '+');
if (aptr == NULL) aptr = strrchr(nexttok, '-');
if (aptr != NULL) {
addin = *aptr;
*aptr = '\0';
if (match(nexttok, ":")) {
if (stack == NULL) {
Printf("Empty array start found.\n");
return 1;
}
if (EvalExpr(&stack, &start) != 1) {
Printf("Bad expression found in array.\n");
return 1;
}
continue;
}
else if (match(nexttok, "+") || match(nexttok, "-")
|| match(nexttok, "*") || match(nexttok, "/")
|| match(nexttok, "(") || match(nexttok, ")")) {
newexp = (struct expr_stack *)MALLOC(sizeof(struct expr_stack));
newexp->oper = *nexttok;
newexp->value = 0;
newexp->next = NULL;
newexp->last = stack;
if (stack) stack->next = newexp;
stack = newexp;
continue;
}
if ((result = sscanf(nexttok, "%d", &value)) != 1) {
// Is name in the parameter list?
kl = (struct property *)HashLookup(nexttok, &verilogparams);
kl = (struct property *)HashLookup(nexttok, &verilogparams);
if (kl == NULL) {
Printf("Array value %s is not a number or a parameter.\n",
nexttok);
return 1;
nexttok);
value = 0;
break;
}
else {
if (kl->type == PROP_STRING) {
result = sscanf(kl->pdefault.string, "%d", &end);
result = sscanf(kl->pdefault.string, "%d", &value);
if (result != 1) {
Printf("Parameter %s has value %s that cannot be parsed"
" as an integer.\n", nexttok,
kl->pdefault.string);
return 1;
" as an integer.\n",
nexttok, kl->pdefault.string);
value = 0;
break;
}
}
else if (kl->type == PROP_INTEGER) {
end = kl->pdefault.ival;
value = kl->pdefault.ival;
}
else if (kl->type == PROP_DOUBLE) {
end = (int)kl->pdefault.dval;
if ((double)end != kl->pdefault.dval) {
Printf("Cannot parse second digit from parameter "
"%s value %g\n", nexttok, kl->pdefault.dval);
return 1;
value = (int)kl->pdefault.dval;
if ((double)value != kl->pdefault.dval) {
Printf("Parameter %s has value %g that cannot be parsed"
" as an integer.\n",
nexttok, kl->pdefault.dval);
value = 0;
break;
}
}
else {
Printf("Parameter %s has unknown type; don't know how"
" to parse.\n", nexttok);
return 1;
Printf("Parameter %s has unknown type; don't know how"
" to parse.\n", nexttok);
value = 0;
break;
}
}
if (aptr != NULL) {
int addval;
*aptr = addin;
if (sscanf(aptr + 1, "%d", &addval) != 1) {
Printf("Unable to parse parameter increment '%s'\n", aptr);
return 1;
}
end += (addin == '+') ? addval : -addval;
}
}
newexp = (struct expr_stack *)MALLOC(sizeof(struct expr_stack));
newexp->oper = '\0';
newexp->value = value;
newexp->next = NULL;
newexp->last = stack;
if (stack) stack->next = newexp;
stack = newexp;
}
wb->start = start;
wb->end = end;
/* In case of error, stack may need cleaning up */
while (stack != NULL) {
newexp = stack;
stack = stack->last;
FREE(newexp);
}
while (!match(nexttok, "]")) {
SkipTokComments(VLOG_DELIMITERS);
if (nexttok == NULL) {
@@ -1128,13 +1288,6 @@ skip_endmodule:
kl->pdefault.ival = 1;
kl->slop.ival = 0;
}
else if (nexttok[0] == '(') {
/* For now, the netgen verilog parser doesn't handle `define f(X) ... */
SkipNewLine(VLOG_DELIMITERS);
FREE(kl->key);
FREE(kl);
kl = NULL;
}
else if (ConvertStringToInteger(nexttok, &ival) == 1) {
/* Parameter parses as an integer */
kl->type = PROP_INTEGER;
@@ -1319,6 +1472,8 @@ skip_endmodule:
rhs = LookupObject(assignname, CurrentCell);
*aptr = '[';
}
else
strcpy(assignroot, nexttok);
}
else {
j = -1;
@@ -1514,7 +1669,7 @@ nextinst:
// Read the pin list
while (nexttok != NULL) {
SkipTokComments(VLOG_DELIMITERS);
SkipTokComments(VLOG_PIN_CHECK_DELIMITERS);
if (match(nexttok, ")")) break;
else if (match(nexttok, ",")) continue;
@@ -1778,54 +1933,6 @@ nextinst:
scan->width = width;
result = GetBus(scan->net, &wb);
if (result == -1) {
/* CHECK: THIS CODE SHOULD BE DELETED, IT IS NOT THE ISSUE */
/* Not bus notation, but check if signal was defined as a bus */
wb.start = wb.end = -1;
minnet = maxnet = -1;
/* Pins should be in index order start->end. Other nodes */
/* should be in order start->end by node number. */
for (bobj = CurrentCell->cell; bobj; bobj = bobj->next) {
if (bobj->type == PORT) {
if ((bptr = strvchr(bobj->name, '[')) != NULL) {
*bptr = '\0';
if (!strcmp(bobj->name, scan->net)) {
*bptr = '[';
if (wb.start == -1)
sscanf(bptr + 1, "%d", &wb.start);
else
sscanf(bptr + 1, "%d", &wb.end);
}
}
}
else if (bobj->type == NODE) {
if ((bptr = strvchr(bobj->name, '[')) != NULL) {
*bptr = '\0';
if (!strcmp(bobj->name, scan->net)) {
if (sscanf(bptr + 1, "%d", &testidx) == 1) {
if (minnet == -1) {
minnet = maxnet = bobj->node;
wb.start = wb.end = testidx;
}
else if (bobj->node < minnet) {
minnet = bobj->node;
wb.start = testidx;
}
else if (bobj->node > maxnet) {
maxnet = bobj->node;
wb.end = testidx;
}
}
}
*bptr = '[';
}
}
}
if (wb.start != -1) result = 0;
}
if (result == 0) {
int match = 0;
int wblen, arraylen;
@@ -1935,7 +2042,25 @@ nextinst:
}
}
else if (portstart != portend) {
Fprintf(stderr, "Error: Single net %s is connected to bus port %s\n",
/* If the name starts with "_noconnect_", then it was an
* auto-generated name that incorrectly assumed a single-bit
* wide signal because it did not have a module prototype.
* Rewrite the noconnect name as an array. This just means
* that the verilog had an empty list "()" and the initial
* assumption was wrong. If not all instances agree on the
* size, then this will eventually generate an error.
*/
if (!strncmp(scan->net, "_noconnect_", 11) &&
(strchr(scan->net, '\[') == NULL) && (width > 1)) {
char *savenet = scan->net;
char *newnet = MALLOC(strlen(scan->net) + 12);
sprintf(newnet, "%s[%d:0]", scan->net, scan->width - 1);
FREE(savenet);
scan->net = newnet;
continue; /* Re-process this entry */
}
else
Fprintf(stderr, "Error: Single net %s is connected to bus port %s\n",
scan->net, scan->name);
}
}
@@ -2103,6 +2228,9 @@ nextinst:
obptr->next = nobj;
HashPtrInstall(nobj->name, nobj, &(CurrentCell->objdict));
/* Ensure that CurrentTail is correct */
if (obptr == CurrentTail) CurrentTail = nobj;
if (LookupObject(scan->net, CurrentCell) == NULL)
Node(scan->net);
join(scan->net, nobj->name);
@@ -2117,7 +2245,7 @@ nextinst:
sobj = sobj->next) {
if (sobj->type == FIRSTPIN) {
if (match(sobj->model.class, obptr->model.class)) {
while (sobj->next->type > FIRSTPIN)
while (sobj->next && (sobj->next->type > FIRSTPIN))
sobj = sobj->next;
/* Stop when reaching the current instance */
if (sobj->type == obptr->type + 1) break;
@@ -2144,6 +2272,7 @@ nextinst:
}
}
}
obptr = obptr->next;
}
else {
Fprintf(stderr, "Error: Instance %s has pin %s which is "
@@ -2242,8 +2371,19 @@ char *ReadVerilogTop(char *fname, int *fnum, int blackbox)
hashfunc = hashcase;
}
InitializeHashTable(&verilogparams, OBJHASHSIZE);
InitializeHashTable(&verilogdefs, OBJHASHSIZE);
if ((hashfile != -1) && (hashfile != *fnum)) {
/* Started a new file, so remove all the parameters and definitions */
RecurseHashTable(&verilogparams, freeprop);
HashKill(&verilogparams);
RecurseHashTable(&verilogdefs, freeprop);
HashKill(&verilogdefs);
hashfile = -1;
}
if (hashfile == -1) {
InitializeHashTable(&verilogparams, OBJHASHSIZE);
InitializeHashTable(&verilogdefs, OBJHASHSIZE);
hashfile = *fnum;
}
definitions = &verilogdefs;
/* Add the pre-defined key "LVS" to verilogdefs */
@@ -2263,10 +2403,6 @@ char *ReadVerilogTop(char *fname, int *fnum, int blackbox)
// Cleanup
while (CellStack != NULL) PopStack(&CellStack);
RecurseHashTable(&verilogparams, freeprop);
HashKill(&verilogparams);
RecurseHashTable(&verilogdefs, freeprop);
HashKill(&verilogdefs);
definitions = (struct hashdict *)NULL;
// Record the top level file.
+110 -86
View File
@@ -62,16 +62,18 @@ proc netgen::convert_to_json {filename lvs_final} {
puts $fjson " \["
set cktval [lindex $value 0]
foreach pin [lrange $cktval 0 end-1] {
puts $fjson " \"$pin\","
set pinstr [string map {"\\" "\\\\"} $pin]
puts $fjson " \"$pinstr\","
}
set pin [lindex $cktval end]
set pin [string map {"\\" "\\\\"} [lindex $cktval end]]
puts $fjson " \"$pin\""
puts $fjson " \], \["
set cktval [lindex $value 1]
foreach pin [lrange $cktval 0 end-1] {
puts $fjson " \"$pin\","
set pinstr [string map {"\\" "\\\\"} $pin]
puts $fjson " \"$pinstr\","
}
set pin [lindex $cktval end]
set pin [string map {"\\" "\\\\"} [lindex $cktval end]]
puts $fjson " \"$pin\""
puts $fjson " \]"
if {$kidx == $nkeys} {
@@ -393,7 +395,7 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
# If argument is a filename then read the list of cells from it;
# otherwise, argument is the list of files itself in quotes or
# braces.
if {![catch {file exists $value}]} {
if {[file exists $value]} {
if {![catch {open $value r} fnf]} {
while {[gets $fnf line] >= 0} {
if {[lindex $line 0] != "#"} {
@@ -532,14 +534,24 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
}
set properr {}
set matcherr {}
set pinsgood -1
set childMismatch 0 ;# 1 indicates black-box child subcircuit mismatch
while {$endval != {}} {
if {$dolist == 1} {
netgen::run -list converge
} else {
netgen::run converge
}
netgen::log echo on
set pinMismatch 0 ;# indicates pin mismatch in top cell
set doCheckFlatten 0
set doFlatten 0
if {[netgen::print queue] == {}} {
set doEquatePins 1 ;# run equate pins on top cell
} else {
set doEquatePins 0 ;# don't run equate pins unless unique match
}
set forceMatch 0 ;# for pin matching
netgen::log echo off
if {[verify equivalent]} {
# Resolve automorphisms by pin and property
if {$dolist == 1} {
@@ -548,96 +560,105 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
netgen::run resolve
}
set uresult [verify unique]
# uresult: -3 : unique with property error
# -2 : equivalent with port errors
# -1 : black box
# 0 : equivalent but not unique
# 1 : unique
if {$uresult == 0} {
netgen::log echo on
netgen::log put " Networks match locally but not globally.\n"
netgen::log put " Probably connections are swapped.\n"
netgen::log put " Check the end of logfile ${logfile} for implicated nodes.\n"
netgen::log echo off
if {$dolist == 1} {
verify -list nodes
} else {
verify nodes
}
# Flatten the non-matching subcircuit (but not the top-level cells)
if {[netgen::print queue] != {}} {
if {([lsearch $noflat [lindex $endval 0]] == -1) &&
([lsearch $noflat [lindex $endval 1]] == -1)} {
netgen::log put " Flattening non-matched subcircuits $endval\n"
netgen::flatten class "[lindex $endval 0] $fnum1"
netgen::flatten class "[lindex $endval 1] $fnum2"
} else {
netgen::log put " Continuing with black-boxed subcircuits $endval\n"
lappend matcherr [lindex $endval 0]"($fnum1)"
lappend matcherr [lindex $endval 1]"($fnum2)"
# Match pins
netgen::log echo off
if {$dolist == 1} {
set result [equate -list -force pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
} else {
set result [equate -force pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
}
if {$result != 0} {
equate classes "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"
}
set pinsgood $result
netgen::log echo on
}
}
set doCheckFlatten 1
} else {
netgen::log echo off
if {$dolist == 1} {
set result [equate -list pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
} else {
set result [equate pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
}
if {$result != 0} {
equate classes "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"
}
# If $uresult == -1 then these are black-box entries and
# $pinsgood should not be set to the resulting value.
if {$uresult > 0} {
set pinsgood $result
}
netgen::log echo on
# Equate pins for black boxes, unique matches (possibly with property
# errors), and unique with port errors
set doEquatePins 1
}
if {$uresult == -1} { ;# black box
set forceMatch 1
} elseif {$uresult == -3} { ;# property error
lappend properr [lindex $endval 0]
} elseif {$uresult == -2} { ;# unmatched pins
set doCheckFlatten 1
}
if {$uresult == 2} {lappend properr [lindex $endval 0]}
} else {
# Flatten the non-matching subcircuit (but not the top-level cells)
if {[netgen::print queue] != {}} {
# not equivalent
netgen::log echo on
# netgen::log put " DEBUG: not equivalent $endval\n"
netgen::log echo off
set doCheckFlatten 1
}
if {$doCheckFlatten} {
# Flatten the non-matching subcircuit (but not the top-level cell,
# or cells explicitly prohibited from flattening)
if {[netgen::print queue] != {}} {
if {([lsearch $noflat [lindex $endval 0]] == -1) &&
([lsearch $noflat [lindex $endval 1]] == -1)} {
netgen::log put " Flattening non-matched subcircuits $endval\n"
netgen::flatten class "[lindex $endval 0] $fnum1"
netgen::flatten class "[lindex $endval 1] $fnum2"
} else {
([lsearch $noflat [lindex $endval 1]] == -1)} {
set doFlatten 1
} else {
netgen::log echo on
netgen::log put " Continuing with black-boxed subcircuits $endval\n"
netgen::log echo off
lappend matcherr [lindex $endval 0]"($fnum1)"
lappend matcherr [lindex $endval 0]"($fnum2)"
# Match pins
netgen::log echo off
if {$dolist == 1} {
set result [equate -list -force pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
} else {
set result [equate -force pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
}
if {$result != 0} {
equate classes "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"
}
set pinsgood $result
netgen::log echo on
lappend matcherr [lindex $endval 1]"($fnum2)"
netgen::flatten prohibit "[lindex $endval 0] $fnum1"
netgen::flatten prohibit "[lindex $endval 1] $fnum2"
set doEquatePins 1
set childMismatch 1
set forceMatch 1
}
}
}
netgen::log echo off
if {$doEquatePins} {
# Match pins
if {$dolist == 1} {
if {$forceMatch} {
set result [equate -list -force pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
} else {
set result [equate -list pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
}
} else {
if {$forceMatch} {
set result [equate -force pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
} else {
set result [equate pins "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"]
}
}
if {$result >= 0} {
equate classes "$fnum1 [lindex $endval 0]" \
"$fnum2 [lindex $endval 1]"
}
# Do not set pinMismatch for black boxes
if {$result < 0} {
if {$result == -1 && [netgen::print queue] != {} && $forceMatch != 1} {
# flatten pin mismatch, but not empty cells (-2) or top cell or
# cells prohibited from flattening.
set doFlatten 1
}
} elseif {[netgen::print queue] == {} && $result == 0} {
set pinMismatch 1
}
}
if {$doFlatten} {
netgen::log echo on
netgen::log put " Flattening non-matched subcircuits $endval\n"
netgen::log echo off
netgen::flatten class "[lindex $endval 0] $fnum1"
netgen::flatten class "[lindex $endval 1] $fnum2"
}
if {$dolist == 1} {
catch {lappend lvs_final $lvs_out}
set lvs_out {}
@@ -646,20 +667,23 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
set endval [netgen::compare hierarchical]
}
}
netgen::log echo off
puts stdout "Result: " nonewline
netgen::log echo on
if {$pinsgood == 0} {
# NOTE: Need to disambiguate these two cases. . .
netgen::log put "Cells failed matching, or top level cell failed pin matching.\n"
netgen::log put "\nFinal result: "
if {$pinMismatch || $childMismatch} {
if {$childMismatch} {
netgen::log put "Subcell(s) failed matching.\n"
}
if {$pinMismatch} {
netgen::log put "Top level cell failed pin matching.\n"
}
} else {
verify only
}
if {$properr != {}} {
netgen::log put "The following cells had property errors:\n " [regsub -all { } $properr "\n "] "\n"
netgen::log put "\nThe following cells had property errors:\n " [regsub -all { } $properr "\n "] "\n"
}
if {$matcherr != {}} {
netgen::log put "The following subcells failed to match:\n " [regsub -all { } $matcherr "\n "] "\n"
netgen::log put "\nThe following subcells failed to match:\n " [regsub -all { } $matcherr "\n "] "\n"
}
if {$dolog} {
netgen::log end
+110 -40
View File
@@ -1056,6 +1056,12 @@ _netgen_flatten(ClientData clientData,
FlattenInstancesOf(repstr, filenum);
}
}
else if (!strcmp(argv, "prohibit") || !strcmp(argv, "deny")) {
tp = GetTopCell(filenum);
Printf("Will not flatten instances of %s in file %s\n", repstr, tp->name);
/* Mark cell as placeholder so it will not be flattened */
tp->flags |= CELL_PLACEHOLDER;
}
else {
Tcl_WrongNumArgs(interp, 1, objv, "class valid_cellname");
return TCL_ERROR;
@@ -1931,9 +1937,17 @@ _netgen_log(ClientData clientData,
switch(index) {
case START_IDX:
LoggingFile = fopen(LogFileName, "w");
if (!LoggingFile) {
Tcl_SetResult(interp, "Could not open log file.", NULL);
return TCL_ERROR;
}
break;
case RESUME_IDX:
LoggingFile = fopen(LogFileName, "a");
if (!LoggingFile) {
Tcl_SetResult(interp, "Could not open log file.", NULL);
return TCL_ERROR;
}
break;
case END_IDX:
fclose(LoggingFile);
@@ -1942,6 +1956,10 @@ _netgen_log(ClientData clientData,
case RESET_IDX:
fclose(LoggingFile);
LoggingFile = fopen(LogFileName, "w");
if (!LoggingFile) {
Tcl_SetResult(interp, "Could not open log file.", NULL);
return TCL_ERROR;
}
break;
case SUSPEND_IDX:
fclose(LoggingFile);
@@ -2095,8 +2113,9 @@ _netcmp_compare(ClientData clientData,
int dohierarchy = FALSE;
int assignonly = FALSE;
int argstart = 1, qresult, llen, result;
int hascontents1, hascontents2;
struct Correspond *nextcomp;
struct nlist *tp;
struct nlist *tp1 = NULL, *tp2 = NULL;
Tcl_Obj *flist = NULL;
if (objc > 1) {
@@ -2139,24 +2158,24 @@ _netcmp_compare(ClientData clientData,
}
else if ((objc - argstart) == 2) {
result = CommonParseCell(interp, objv[argstart], &tp, &fnum1);
result = CommonParseCell(interp, objv[argstart], &tp1, &fnum1);
if (result != TCL_OK) return TCL_ERROR;
else if (fnum1 == -1) {
Tcl_SetResult(interp, "Cannot use wildcard with compare command.\n",
NULL);
return TCL_ERROR;
}
name1 = tp->name;
name1 = tp1->name;
argstart++;
result = CommonParseCell(interp, objv[argstart], &tp, &fnum2);
result = CommonParseCell(interp, objv[argstart], &tp2, &fnum2);
if (result != TCL_OK) return TCL_ERROR;
else if (fnum2 == -1) {
Tcl_SetResult(interp, "Cannot use wildcard with compare command.\n",
NULL);
return TCL_ERROR;
}
name2 = tp->name;
name2 = tp2->name;
if (dohierarchy) {
RemoveCompareQueue();
@@ -2195,12 +2214,38 @@ _netcmp_compare(ClientData clientData,
ConvertGlobals(name2, fnum2);
}
CreateTwoLists(name1, fnum1, name2, fnum2, dolist);
while (PrematchLists(name1, fnum1, name2, fnum2) > 0) {
Fprintf(stdout, "Making another compare attempt.\n");
Printf("Flattened mismatched instances and attempting compare again.\n");
CreateTwoLists(name1, fnum1, name2, fnum2, dolist);
tp1 = LookupCellFile(name1, fnum1);
tp2 = LookupCellFile(name2, fnum2);
hascontents1 = HasContents(tp1);
hascontents2 = HasContents(tp2);
if (hascontents1 && !hascontents2 && (tp2->flags & CELL_PLACEHOLDER)) {
Fprintf(stdout, "\nCircuit 2 cell %s is a black box; will not flatten "
"Circuit 1\n", name2);
}
else if (hascontents2 && !hascontents1 && (tp1->flags & CELL_PLACEHOLDER)) {
Fprintf(stdout, "\nCircuit 1 cell %s is a black box; will not flatten "
"Circuit 2\n", name1);
}
else if (hascontents1 || hascontents2) {
FlattenUnmatched(tp1, name1, 1, 0);
FlattenUnmatched(tp2, name2, 1, 0);
DescribeContents(name1, fnum1, name2, fnum2);
while (PrematchLists(name1, fnum1, name2, fnum2) > 0) {
Fprintf(stdout, "Making another compare attempt.\n");
Printf("Flattened mismatched instances and attempting compare again.\n");
FlattenUnmatched(tp1, name1, 1, 0);
FlattenUnmatched(tp2, name2, 1, 0);
DescribeContents(name1, fnum1, name2, fnum2);
}
}
else { /* Two empty subcircuits */
Fprintf(stdout, "\nCircuit 1 cell %s and Circuit 2 cell %s are black"
" boxes.\n", name1, name2);
}
CreateTwoLists(name1, fnum1, name2, fnum2, dolist);
// Return the names of the two cells being compared, if doing "compare
// hierarchical". If "-list" was specified, then append the output
@@ -2456,39 +2501,37 @@ _netcmp_run(ClientData clientData,
ExhaustiveSubdivision = 1;
while (!Iterate() && !InterruptPending);
automorphisms = VerifyMatching();
if (automorphisms == -1)
Fprintf(stdout, "Netlists do not match.\n");
else if (automorphisms == 0)
Fprintf(stdout, "Netlists match uniquely.\n");
else {
if (automorphisms > 0) {
// First try to resolve automorphisms uniquely using
// property matching
automorphisms = ResolveAutomorphsByProperty();
if (automorphisms == 0)
Fprintf(stdout, "Netlists match uniquely.\n");
else if (automorphisms > 0) {
if (automorphisms > 0) {
// Next, attempt to resolve automorphisms uniquely by
// using the pin names
automorphisms = ResolveAutomorphsByPin();
}
if (automorphisms == 0)
Fprintf(stdout, "Netlists match uniquely.\n");
else if (automorphisms > 0) {
if (automorphisms > 0) {
// Anything left is truly indistinguishable
Fprintf(stdout, "Netlists match with %d symmetr%s.\n",
automorphisms, (automorphisms == 1) ? "y" : "ies");
while ((automorphisms = ResolveAutomorphisms()) > 0);
while (ResolveAutomorphisms() > 0);
}
if (automorphisms == -1)
Fprintf(stdout, "Netlists do not match.\n");
else
Fprintf(stdout, "Circuits match correctly.\n");
}
if (PropertyErrorDetected) {
Fprintf(stdout, "There were property errors.\n");
PrintPropertyResults(dolist);
if (automorphisms == -1)
Fprintf(stdout, "Netlists do not match.\n");
else if (automorphisms == -2)
Fprintf(stdout, "Netlists match uniquely with port errors.\n");
else {
if (automorphisms == 0)
Fprintf(stdout, "Netlists match uniquely");
else
Fprintf(stdout, "Netlists match with %d symmetr%s",
automorphisms, (automorphisms == 1) ? "y" : "ies");
if (PropertyErrorDetected) {
Fprintf(stdout, " with property errors.\n");
PrintPropertyResults(dolist);
}
else
Fprintf(stdout, ".\n");
}
disable_interrupt();
}
@@ -2506,8 +2549,14 @@ _netcmp_run(ClientData clientData,
/* all, or no option. */
/* Formerly: v */
/* Results: */
/* For only, equivalent, unique: Return 1 if */
/* verified, zero if not. */
/* For only, equivalent, unique: Return */
/* 1: verified */
/* 0: not verified */
/* -1: no elements or nodes */
/* -3: verified with property error */
/* equiv option */
/* -2: pin mismatch */
/* */
/* Side Effects: */
/* For options elements, nodes, and all without */
/* option -list: Write output to log file. */
@@ -2601,13 +2650,21 @@ _netcmp_verify(ClientData clientData,
else
Fprintf(stdout, "Netlists do not match.\n");
}
else if (automorphisms == -2) {
if (index == EQUIV_IDX)
Tcl_SetObjResult(interp, Tcl_NewBooleanObj(1));
else if (index == UNIQUE_IDX)
Tcl_SetObjResult(interp, Tcl_NewIntObj(-2));
else if (index > 0)
Fprintf(stdout, "Circuits match uniquely with port errors.\n");
}
else {
if (automorphisms) {
if (index == EQUIV_IDX)
Tcl_SetObjResult(interp, Tcl_NewIntObj((int)automorphisms));
else if (index == UNIQUE_IDX)
Tcl_SetObjResult(interp, Tcl_NewBooleanObj(0));
else
else if (index > 0)
Printf("Circuits match with %d symmetr%s.\n",
automorphisms, (automorphisms == 1) ? "y" : "ies");
}
@@ -2616,11 +2673,13 @@ _netcmp_verify(ClientData clientData,
if (PropertyErrorDetected == 0)
Tcl_SetObjResult(interp, Tcl_NewBooleanObj(1));
else
Tcl_SetObjResult(interp, Tcl_NewIntObj(2));
Tcl_SetObjResult(interp, Tcl_NewIntObj(-3));
}
else {
else if (index > 0) {
Fprintf(stdout, "Circuits match uniquely.\n");
if (PropertyErrorDetected != 0)
if (PropertyErrorDetected == 0)
Fprintf(stdout, ".\n");
else
Fprintf(stdout, "Property errors were found.\n");
}
}
@@ -3043,7 +3102,11 @@ _netcmp_equate(ClientData clientData,
tp1->flags |= CELL_PLACEHOLDER;
tp2->flags |= CELL_PLACEHOLDER;
}
else {
else if (doforce != TRUE) {
/* When doforce is TRUE, ElementClass has been set to NULL
* even though circuits contain elements, so this message
* is not correct.
*/
Fprintf(stdout, "Equate pins: cell %s and/or %s "
"has no elements.\n", name1, name2);
/* This is not necessarily an error, so go ahead and match pins. */
@@ -3075,6 +3138,13 @@ _netcmp_equate(ClientData clientData,
else if (result > 0) {
Fprintf(stdout, "Cell pin lists are equivalent.\n");
}
else if (result == -1) {
Fprintf(stdout, "Cell pin lists for %s and %s do not match.\n",
name1, name2);
}
else if (result == -2) {
Fprintf(stdout, "Attempt to match empty cell to non-empty cell.\n");
}
else {
Fprintf(stdout, "Cell pin lists for %s and %s altered to match.\n",
name1, name2);