mirror of
https://github.com/RTimothyEdwards/netgen.git
synced 2026-08-22 14:07:07 +02:00
Compare commits
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97058c5017 | ||
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625e043eff | ||
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aa120460d0 | ||
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6ceeddf096 | ||
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42b1acc564 | ||
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6d6da9cf5c |
+42
-6
@@ -259,13 +259,16 @@ int flattenInstancesOf(char *name, int fnum, char *instance)
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struct objlist *ChildObjList, *ChildListEnd;
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struct objlist *ChildStart, *ChildEnd, *ParentEnd, *ParentNext;
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struct nlist *ThisCell;
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struct nlist *ChildCell;
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struct nlist *ChildCell;
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struct objlist *tmp, *ob2, *ob3;
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int notdone, rnodenum;
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char tmpstr[1024];
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int nextnode, oldmax, numflat = 0;
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int notdone, rnodenum;
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char tmpstr[1024];
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int nextnode, oldmax, numflat = 0;
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struct objlist *myObject_p, *myPort_p;
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struct objlist *myFirstPin_p, *myPin_p;
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int myDeleteCount = 0;
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#if !OLDPREFIX
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int prefixlength;
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int prefixlength;
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#endif
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if (name == NULL) {
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@@ -599,6 +602,38 @@ int flattenInstancesOf(char *name, int fnum, char *instance)
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}
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CacheNodeNames(ThisCell);
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ThisCell->dumped = 1; /* indicate cell has been flattened */
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// Remove disconnected ports.
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// Fprintf(stdout, "DEBUG: check pins for %s of %d\n", name, fnum);
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myFirstPin_p = NULL;
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// Save first pin definition so we don't have to search for each port
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for (myObject_p = ThisCell->cell; myObject_p != NULL; myObject_p = myObject_p->next) {
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if (myObject_p->type >= FIRSTPIN) {
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myFirstPin_p = myObject_p;
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break;
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}
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}
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if (myFirstPin_p != NULL) { // Not a black box. Black boxes contain no pins.
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// For each port, check for pin connection. If none, mark for deletion.
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// Assumes that all ports occur at the beginning of the list
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for (myPort_p = ThisCell->cell; myPort_p != NULL && IsPort(myPort_p);
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myPort_p = myPort_p->next ) {
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for (myPin_p = myFirstPin_p; myPin_p != NULL; myPin_p = myPin_p->next) {
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if (myPort_p->node == myPin_p->node) { // only need to find one connection
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break;
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}
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}
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if (myPin_p == NULL) { // mark disconnected ports
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myDeleteCount++;
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myPort_p->node = -2;
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}
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}
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if (myDeleteCount > 0) { // delete disconnected ports
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CleanupPins(name, fnum);
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}
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}
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return numflat;
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}
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@@ -1582,7 +1617,8 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
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}
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}
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else {
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match = 0;
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// Apply recursive flattening when a cell exists in
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// one circuit but not the other.
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break;
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}
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}
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+5
-5
@@ -567,7 +567,8 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
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netgen::flatten class "[lindex $endval 1] $fnum2"
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} else {
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netgen::log put " Continuing with black-boxed subcircuits $endval\n"
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lappend matcherr [lindex $endval 0]
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lappend matcherr [lindex $endval 0]"(1)"
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lappend matcherr [lindex $endval 1]"(2)"
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# Match pins
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netgen::log echo off
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if {$dolist == 1} {
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@@ -609,16 +610,15 @@ proc netgen::lvs { name1 name2 {setupfile setup.tcl} {logfile comp.out} args} {
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} else {
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# Flatten the non-matching subcircuit (but not the top-level cells)
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if {[netgen::print queue] != {}} {
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if {([lsearch $noflat [lindex $endval 1]] == -1) &&
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if {([lsearch $noflat [lindex $endval 0]] == -1) &&
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([lsearch $noflat [lindex $endval 1]] == -1)} {
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netgen::log put " Flattening non-matched subcircuits $endval\n"
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netgen::flatten class "[lindex $endval 0] $fnum1"
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netgen::flatten class "[lindex $endval 1] $fnum2"
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} else {
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netgen::log put " Continuing with black-boxed subcircuits $endval\n"
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lappend matcherr [lindex $endval 0]
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netgen::log put " Continuing with black-boxed subcircuits $endval\n"
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lappend matcherr [lindex $endval 0]
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lappend matcherr [lindex $endval 0]"(1)"
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lappend matcherr [lindex $endval 1]"(2)"
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# Match pins
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netgen::log echo off
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if {$dolist == 1} {
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