Merge branch 'master' into netgen-1.5

Added back a correction that did not get made in this code base
and so didn't make it into the commit. Handles implicit pins in verilog.
2026-08-25 07:27:44 +02:00 · 2020-06-17 03:00:38 -04:00 · 2020-06-16 17:16:30 -04:00 · 2020-06-16 15:56:59 -04:00 · 2020-06-16 12:52:29 -04:00
3 changed files with 11 additions and 8 deletions
@@ -1 +1 @@
-1.5.147
+1.5.148
@@ -1786,7 +1786,7 @@ nextinst:
 	       // Net is bit-sliced across array of instances.

 	       if (wb.start > wb.end) {
-		  char *bptr, *cptr = NULL, cchar, *netname;
+		  char *bptr = NULL, *cptr = NULL, cchar, *netname;
 		  unsigned char is_bundle = 0;
 		  struct bus wbb;

@@ -1918,11 +1918,15 @@ nextinst:
 		  scan = scan->next;
 	       }
 	       if (scan == NULL) {
-		  Fprintf(stderr, "Error:  No match in call for pin %s\n", obpinname);
-		  break;
-	       }
+		  char localnet[100];

-	       if (GetBus(scan->net, &wb) == 0) {
+		  /* Assume an implicit unconnected pin */
+		  sprintf(localnet, "_noconnect_%d_", localcount++);
+		  Node(localnet);
+		  join(localnet, obptr->name);
+		  Fprintf(stderr, "Note:  Implicit pin %s\n", obpinname);
+	       }
+	       else if (GetBus(scan->net, &wb) == 0) {
 		   char *bptr2;
 		   char *scanroot;
 		   scanroot = strsave(scan->net);
@@ -2982,8 +2982,7 @@ _netcmp_equate(ClientData clientData,
 	    else {
 		Fprintf(stdout, "Equate pins:  cell %s and/or %s "
 			"has no elements.\n", name1, name2);
-		Tcl_SetObjResult(interp, Tcl_NewBooleanObj(0));
-		return TCL_OK;
+		/* This is not necessarily an error, so go ahead and match pins. */
 	    }
 	 }
 	 if (ElementClasses == NULL) {
Author	SHA1	Message	Date
Tim Edwards	1428580109	Merge branch 'master' into netgen-1.5	2020-06-17 03:00:38 -04:00
Tim Edwards	fb0e1d10b0	Added back a correction that did not get made in this code base and so didn't make it into the commit. Handles implicit pins in verilog.	2020-06-16 17:16:30 -04:00
Tim Edwards	6f81e1d294	Removed a restriction on the "equate pins" command such that pins are matched on circuits that have no elements. This condition does not necessarily indicate an error, and matching pins has no adverse affect (while refusing to match them certainly can).	2020-06-16 15:56:59 -04:00
Tim Edwards	cec6d89474	Corrected an uninitialized variable error in the verilog reading code that produces a segfault condition.	2020-06-16 12:52:29 -04:00
@@ -1 +1 @@
 .5.147
 .5.148