introduced in revision 150 can result in an incorrect result
reporting a bad match where the match is actually good (as proven
by running the full symmetry breaking on the same netlist).
Because the fast symmetry breaking is orders of magnitude faster
for large circuits, and because the false positive result appears
to be rare, I have introduced a command "symmetry" to switch
methods between fast and full. So fast symmetry breaking can be
run unless the result fails on symmetry breaking, in which case
the method can be switched to full to see if the problem is a
false positive or not. This is not an ideal solution, and some
investigation is needed to determine if there is a way to apply
fast symmetry breaking without encountering a false positive
error.
with the file number, so that it can get confused between libraries.
Also made a fix to coerce one cell class to be forced to be the
same in both circuits under some circumstances.
the top level circuits to be declared matching with no errors even
though the pins do not match. "proxy pins" are fine for subcells
to detect cases where one subcell has an unused pin and the matching
subcell does not declare it, but that should not be allowed on the
top level, as it cannot be known whether the pin is unused or not.
are matched on circuits that have no elements. This condition
does not necessarily indicate an error, and matching pins has no
adverse affect (while refusing to match them certainly can).
in an "include" statement in either SPICE or verilog. Modified pin
matching behavior to force cells in both netlists to be marked as
black-box entries if either one is marked as a black-box entry (this
may not be needed, but shouldn't do any harm, either).
a different way of treating "black box" cells. Even when the
"-blackbox" option is specified, any cell that has no definition
will be treated as a black box. This allows comparison of a
black-box netlist against a non-black-box netlist, such as a
verilog netlist vs. a SPICE netlist, without forcing the black-box
attribute on the SPICE netlist. Then, if the SPICE netlist
contains cells without elements such as fill/decap/tap cells,
they can be flattened and removed instead of forcing an error or
requiring the use of "ignore".
<col2_width>" to set the output format width, to avoid the fixed column
widths of 41 characters which can truncate long strings in the output
such as deep cell hierarchies. This command can be placed in the setup
script to widen the output columns to accomodate the result (to-do:
provide an "auto" mode to automatically determine the best width).
"prefix" with the specified path during install, so that netgen can
be installed in a separate location to be migrated to the final
install location, without appending the entire install path to
DESTDIR.
they are converted to the double-backslash escape that is the proper
JSON syntax for backslashes, instead of being removed, which changes
the name and can be confusing.
handle verilog syntax. Also: Added SPICE voltage and current
sources as separate classes (as opposed to being converted to
subcircuits, which was how they were previously handled). That
allowed voltage sources to be checked for zero value and removed
by shorting the ends together, as was being done for zero value
resistors (note that like zero-value resistors, removal is only
done if removing the component makes a better match than leaving
it in). In particular, yosys has SPICE netlist output that
converts equality assignments ("assign a = b") into zero-value
voltage sources, so these components need to be treated as
non-physical elements.
the possibility that a device (e.g., resistor or capacitor) may
not be a semiconductor device (in other words, a parasitic or
ideal device), and therefore uses "value" but not width and
length, and therefore "value" is a critical property to merge
both in series and parallel. Corrected the series/parallel
network optimization to prevent it from setting both M and S
records > 1 on the same device (which is ambiguous). To try
to get number of devices to match, where there are both series
and parallel devices, they will be merged across the critical
property early (before property matching).
in verilog net names, which are apparently legal in verilog but not
in python strings (if not escaped). This is somewhat critical for
running the LVS GUI as yosys can generate backslashes in generated
net names in the synthesized netlist.
some problems stemming from comparing a case-sensitive netlist
against a case-insensitive one. Verilog netlist reading does
not yet have support for macros other than "`include", and it
does not yet have support for bit vectors constructed with
braces ({}).
calls "equate pins". This could fail because the routine that forces
uniqueness of pins was being called by the "compare" command but
outside of PinMatch. Fixed by duplicating the call to force uniqueness
of pins inside the "equate" function. Redundant calls should not
matter as uniqueness is resolved on the first call and subsequent calls
will need no further action.
be specified as "nosetup" if the "lvs" command is being called
interactively from a terminal or as part of a larger script where
setup commands have been issued prior to running the "lvs" script.
Similarly, the log file can be specified as "nolog" to prevent any
log file from being generated.
time warnings and errors. Removed the "-lazy" option from the
Tcl load command, which is not needed when the stubs libraries
are compiled in correctly, and which causes issues on some
systems (e.g., Mac OS). Thanks to Matt Guthaus for the patch.
for subcircuits (.subckt ... .ends pair with cellname and pin names
and pin order, but no contents) are automatically treated as black-
box circuits if found and if the "-blackbox" option is passed to the
"lvs" (scripted) command. The "equate pins" command can be used
outside of a comparison to force two circuits (black-box or
otherwise) to be matched by pin name (if not a black-box circuit,
then this is a provisional name match, as a circuit comparison will
order based on connectivity first, not pin names). So two sets of
black-box circuit libraries can be used as long as their pin names
match. One hack added to ignore the "!" at the end of global names
when comparing pin names for matching. Otherwise, pin names must
compare by case-insensitive string match.
documentation, and behaves as intended, which is that "-all" is
not a standalone option but is itself an optional qualifier to
the "cells <valid_cellname>" command. So the options are
"cells <valid_cellname>" and "cells -all <valid_cellname>".
treat empty subcircuits as blackbox cells automatically without
requiring specific callse to "model <cell> blackbox" for each.
Enabled in LVS script by giving option "-blackbox" at the end
of the LVS command.
making any subcircuit serializable by using the new command option
"property (device) serial|parallel enable|disable". Note that as
of this commit, serial device detection is enabled but serial
networks are not collapsed for matching, which will tend to lead
to property errors in serial devices until this code is added,
which should be in a day or two.
'ignore class', but removes instances of the specified class whose
pins are shorted together. Currently requires that all pins must
be shorted together.
leading '/' of pin names and therefore failing to print anything;
(2) Corrected 'addproxies', which was ending abruptly at the end of
a circuit's object list, such that if an instance needing proxy pins
added was the last object in the circuit, it would not get the proxy
pins added, and therefore would fail LVS.
"permute default" by (1) handling the usual case for MOSFETs
(resistors and adding in parallel not yet implemented), and
(2) being done automatically when no setup script is specified.
Tim Edwards