a spice netlist falls exactly on the last non-null position of the
input buffer after the buffer has been expanded to accept more
input data, then the next line gets read in automatically, and
the newline gets treated as whitespace and not a newline.
to strdtok() can differentiate between reading verilog and reading
SPICE. Otherwise, SPICE containing the (dubious) syntax of using
backslashes in names will get treated as a verilog name with
verilog backslash notation, with generally undesirable results.
When called from the SPICE reading routine, backslashes are
treated as-is and not as verilog notation.
(1) When a comment line follows a ".subckt" line, and the comment
line is empty or all whitespace, then the following line would
be ignored. This condition appears to be very specific and
was solved simply by detecting it and handling it.
(2) Occasionally the "M" parameter of a subcircuit will be recorded
as type double, and this was not being anticipated by the code
that checks if "M=1" matches a corresponding entry with no "M"
parameter. Simple fix to check the condition where the "M"
parameter is type double.
with IRSIM including recent changes made to support multiple device
types using the subcircuit "x" component type. This requires
reading in a .prm file, which incidentally can be used with any
SPICE file to inform netgen of the specific component type of any
model defined as a subcircuit.
response to Mitch Bailey's github issue #82:
(1) When skipping comments, skip the contents of "(* ... *)"
delimiters as well as "/* ... */" delimiters.
(2) When checking for qflow's "\abcd\" names (final space
replaced with a backslash for SPICE compatibility of
names), make sure that the last "\" is followed by end-
of-string. Otherwise names like "\a\bcd " will fail to
parse correctly.
This is done by treating the loop variable as a temporary parameter
that is valid only inside the loop, and changing the parameter
value on each loop iteration. The file stream position is used
to iterate the loop with calls to fseek() and ftell(), so that the
input tokenizer continues to work within loops.
definitions are handled correctly. Also: Added code to evaluate
simple expressions for array bounds. Previously the parser could
handle a value followed by "+" or "-" and a constant. Now it can
handle all basic arithmetic.
for file extensions is greedy and picks the first matching extension
starting at the front of the string, such that, e.g., "file.ext.spice"
is interpreted as a ".ext" file and not a ".spice" file.
to include type CLASS_MODULE in the list of types to descend into,
since "module" (black-box) types need to be checked for pin
matching even if they have no contents. This allows two verilog
netlists to be compared against each other.
definitions: Now correctly parses everything from the definition
name to the end of line as the definition value. Also: The
search for definitions in the body of the text does not reject
non-alphanumerics "_" and "$" in the definition name, without
which definition names containing those characters will go
unrecongized. Have not yet extended this to multi-line definition
values.
verilog parser. The parser should now be able to handle any
conditionals anywhere in the verilog code. Also a bug was found
in the code that handles "a = b" assignments, and corrected.
code using the backtick expression. Also expanded the parsing of
"ifdef", "ifndef", and "endif" to include "elsif" and "else". All
forms of "if" statements should now be handled, since verilog does
not define boolean expressions in ifdef operators like most languages
do.
SPICE and verilog, in spite of the syntactical differences, to
account for the trick that qflow uses to replace the trailing space
in a verilog backslash-escaped name with a second backslash to get
a SPICE-compatible name that can be easily converted back to its
original verilog name without loss of information. What this means
is that verilog can read SPICE files containing verilog names (which
is illegal SPICE) and verilog files containing hacked-backslash
names (which is illegal verilog). This should be mostly harmless
although the wisdom of it is surely questionable.
handle verilog syntax. Also: Added SPICE voltage and current
sources as separate classes (as opposed to being converted to
subcircuits, which was how they were previously handled). That
allowed voltage sources to be checked for zero value and removed
by shorting the ends together, as was being done for zero value
resistors (note that like zero-value resistors, removal is only
done if removing the component makes a better match than leaving
it in). In particular, yosys has SPICE netlist output that
converts equality assignments ("assign a = b") into zero-value
voltage sources, so these components need to be treated as
non-physical elements.
perfect). Given the complexities of the verilog language, the simple
strtok() tokenizer used by the SPICE parser is not sufficient. Wrote
a better tokenizer that can distinguish between whitespace and
functional tokens like parentheses, semicolons, etc., which are tokens
themselves but also token separators.
some problems stemming from comparing a case-sensitive netlist
against a case-insensitive one. Verilog netlist reading does
not yet have support for macros other than "`include", and it
does not yet have support for bit vectors constructed with
braces ({}).
as failing on certain compilers. This undoubtedly reflects some
change in gcc or the OS setup, but since modern compilers should
be able to figure out for themselves when to inline a subroutine
(or not), the inline hint is somewhat arcane and unnecessary.
D. Mitch Bailey
R. Timothy Edwards