before its component cells, and the component cells are read in as
SPICE netlists. Then the original verilog cell and its instances
need to have pins reordered to match the subcircuit definition in
the SPICE netlist. Otherwise, when verilog and SPICE netlists are
mixed, the order in which the files are read is critical, and
failures due to reading out-of-order are very obscure and nearly
impossible to debug.
to a single net (as can be done with assignments in verilog or with
zero-voltage sources or zero-value resistors in SPICE). Corrected
an error in the SPICE netlist reader that prevented the proper use
of zero-voltage sources as net splitters.
marked as unneeded, so I simply removed the code rather than
debug the issue, which was that buses got the delimeters erased
for checking but never put back again. Also: Modified the verilog
reading code so that if an empty set "()" is given for a pin, then
the initial proxy, which is a single net with the name prefix
"_noconnect_", can be promoted to a bus if further processing
reveals it to be a bus and not a single-bit signal.
This fixes crash on macos due to wrong hash() being linked in.
It also makes sure that proper function defs are declared and available
(as required by C99) to make compile possible in newer compilers (e.g.
Apple clang) and to some extend prevent similar linkage issues happening
again.
format files to the SPICE parser, so that netgen can be run
directly on a testbench file and not generate errors due to
statements in the control block.
black-box circuits, especially those coming from verilog netlists
where a pin does not need to be declared and is implicitly floating.
This prevents the need to have an explicit black-box entry for any
verilog module that may have an instance that does not declare all
the pin connections. Also corrected an error which causes mysterious
failures if a verilog netlist is read before a SPICE netlist,
because the former gets hashed case-sensitive and the latter changes
the hashing to case-insensitive. Modified to force the SPICE
netlist to be treated case-sensitive, which may cause errors, but
is consistent with the reverse order handling, and doesn't cause
unexplained errors.
long run-times even when there are no properties to check. Corrected
a problem with SPICE and verilog netlist reading which arbitrarily
replaces file extensions even when a file extension is given,
resulting in reading the wrong file.
to include type CLASS_MODULE in the list of types to descend into,
since "module" (black-box) types need to be checked for pin
matching even if they have no contents. This allows two verilog
netlists to be compared against each other.
in an "include" statement in either SPICE or verilog. Modified pin
matching behavior to force cells in both netlists to be marked as
black-box entries if either one is marked as a black-box entry (this
may not be needed, but shouldn't do any harm, either).
handle verilog syntax. Also: Added SPICE voltage and current
sources as separate classes (as opposed to being converted to
subcircuits, which was how they were previously handled). That
allowed voltage sources to be checked for zero value and removed
by shorting the ends together, as was being done for zero value
resistors (note that like zero-value resistors, removal is only
done if removing the component makes a better match than leaving
it in). In particular, yosys has SPICE netlist output that
converts equality assignments ("assign a = b") into zero-value
voltage sources, so these components need to be treated as
non-physical elements.
CDL syntax) parameters that have values which are multi-word and
space separated (who the hell comes up with these things?). One
can presumably safely assume that additional pin names are not
intermixed with parameters, so now if a multi-token parameter
value is encountered, the first word is taken as the value and
the remaining words are ignored, generating a warning message.
Since I have no idea what these values are used for, I cannot say
with certainty whether or not this would break LVS, but in the
test case given to me, the parameter had no impact on LVS, but
was apparently an annotation for the layout editor.
some problems stemming from comparing a case-sensitive netlist
against a case-insensitive one. Verilog netlist reading does
not yet have support for macros other than "`include", and it
does not yet have support for bit vectors constructed with
braces ({}).
from a ".include" line by trying alternate extensions. This
should be discouraged, as it happened that a file included
"name.defparams", a file that didn't exist, and instead of calling
out the missing file, it recast it to "name.spice" and caused it
to drop into an infinite loop. Oops.
for subcircuits (.subckt ... .ends pair with cellname and pin names
and pin order, but no contents) are automatically treated as black-
box circuits if found and if the "-blackbox" option is passed to the
"lvs" (scripted) command. The "equate pins" command can be used
outside of a comparison to force two circuits (black-box or
otherwise) to be matched by pin name (if not a black-box circuit,
then this is a provisional name match, as a circuit comparison will
order based on connectivity first, not pin names). So two sets of
black-box circuit libraries can be used as long as their pin names
match. One hack added to ignore the "!" at the end of global names
when comparing pin names for matching. Otherwise, pin names must
compare by case-insensitive string match.
treat empty subcircuits as blackbox cells automatically without
requiring specific callse to "model <cell> blackbox" for each.
Enabled in LVS script by giving option "-blackbox" at the end
of the LVS command.
'ignore class', but removes instances of the specified class whose
pins are shorted together. Currently requires that all pins must
be shorted together.
include calculations of effective width due to the addition of
width of multiple device instances in parallel. The original
behavior of splitting all "M=" devices into individual instances
has been effectively inverted, instead combining all parallel
devices of the same class into one, with multiple property
records for devices with non-matching properties (e.g., width,
length, etc.). Property matching combines devices with different
"critical properties" (e.g., FET gate width) if these are defined
in the setup using the "property merge" command.
Not yet done: Matching of multiple property records when
critial properties are not defined, handling of critical properties
that combine in parallel instead of simple addition, handling of
devices that combine in series, and the combination of non-critical
properties (e.g., source and drain area, although these are usually
removed from matching).
based on properties that can be traded with number of devices,
such as MOSFET width, by merging. This initial implementation
is somewhat limited, only dealing with properties that merge
by summing. Only devices that do not match at all in the other
circuit will be considered for merging. The feature includes
a command option "property ... merge ..." that allows control
over which devices can and cannot be merged.
variables to iterate over hash table contents. This led to the
inability to nest hash table iterators. Fixed by defining a
wrapper structure that holds the actual hash table plus the size
and iterator indexes. Not only does this solve the nesting
problem, but it also avoids the need to pass the hash table size
on every call, and that reduces the number of ways a hash table
subroutine can go wrong (e.g., cannot access the table out of
bounds simply by passing a size that is larger than was used to
initialize the table).
comparisons between, duplicate cells (cells with the same netlist
that may have more than one name in a circuit, or which for some
reason appear with the same name more than once in a netlist).
Added more checks to the list prematching, which prevents various
troubles with cells having a mismatched hierarchy. Added a
command option to "flatten class" to flatten instances only within
a specific cell. Corrected one error in the pin matching routine.
Added a check in the pin matching routine to look for pins that
have been found to be no-connects after cleaning up the pin lists
of the children of that cell.
after ".ends" (seems to be unique to that situation). Also,
corrected a segfault caused by a cell definition containing
only components that are uninstantiated subcircuits (recently
added code makes references to CurrentCell without checking if
it exists).
Tim Edwards
D. Mitch Bailey
Kamyar Mohajerani
Alessandro De Laurenzis