af7bc39bbf
Added tilde expansion handling for .INCLUDE statements to the
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SPICE netlist read routine.
2017-06-19 12:38:27 -04:00
5cd68b9ef1
Merge branch 'master' into work
2017-06-18 22:48:13 -04:00
07788e7501
Update at Sun Jun 18 22:48:11 EDT 2017 by tim
2017-06-18 22:48:11 -04:00
24cc7d0c94
Update to add "property parallel none" command option.
2017-06-18 22:47:51 -04:00
dbcd36d3ec
Merge branch 'master' into work
2017-05-15 16:31:03 -04:00
25c17abb70
Update at Mon May 15 16:31:00 EDT 2017 by tim
2017-05-15 16:31:00 -04:00
fd019b4afd
Corrected the same error as a few commits back that causes a message
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about property errors to show up, not due to property errors, but
due to proxy pins being inserted in the middle of a device record.
However, the first one was fixed for the case of proxy pins being
added to circuit 1, but the same fix was not made for the opposite
case of proxy pins being added to circuit 2. This commit corrects
that omission.
2017-05-15 16:29:12 -04:00
cdfd74bac4
Removed old comment from code referring to the development state.
2017-05-08 21:00:43 -04:00
dd9e02c5f3
Merge branch 'master' into work
2017-05-08 20:57:01 -04:00
26cd16f3ff
Update at Mon May 8 20:56:58 EDT 2017 by tim
2017-05-08 20:56:58 -04:00
ccdd47bc0b
Corrected rare case where a cell that is flattened is the first
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instance in a cell, and is empty, and causes the cell contents
to be nulled out.
2017-05-08 20:55:58 -04:00
ace1c28507
Corrected an error placing proxy pins after the first pin of the
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first object if the (presumably top-level) cell has no pins
(top-level cells not in a subcircuit definition satisfy this
condition).
2017-05-05 21:08:09 -04:00
5e9635e05f
Merge branch 'master' into work
2017-05-05 17:36:32 -04:00
5c168946e3
Update at Fri May 5 17:36:29 EDT 2017 by tim
2017-05-05 17:36:29 -04:00
1471f0c09f
Corrected error in combining property records of serial devices.
2017-05-05 17:35:57 -04:00
73b81fcfe3
Merge branch 'master' into work
2017-04-25 08:47:58 -04:00
b083a6df7c
Update at Tue Apr 25 08:47:57 EDT 2017 by tim
2017-04-25 08:47:57 -04:00
2b5a96500c
Corrected the .gitignore file, which was apparently missed when
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version 1.5 was first created in git.
2017-04-25 08:47:33 -04:00
66f94b47e6
Merge branch 'master' into work
2017-03-06 14:01:26 -05:00
09532ee628
Update at Mon Mar 6 14:01:25 EST 2017 by tim
2017-03-06 14:01:25 -05:00
2b7d416a41
A few corrections to the JSON format output.
2017-03-06 14:01:14 -05:00
090e9e122a
Merge branch 'master' into work
2017-03-03 09:11:54 -05:00
67f1c1a2e9
Update at Fri Mar 3 09:11:52 EST 2017 by tim
2017-03-03 09:11:52 -05:00
a7dcb4ef45
Corrected new JSON file output format from netgen.
2017-03-03 09:11:30 -05:00
a0f1b4cc92
Merge branch 'master' into work
2017-02-27 09:36:54 -05:00
b5d5496e40
Update at Mon Feb 27 09:36:52 EST 2017 by tim
2017-02-27 09:36:52 -05:00
7cac67c81b
Corrected an error in the property match subroutine that was failing
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to stop at the end of an instance record without properties, leading
to strange errors where netgen declares "There were property errors"
but does not print any errors (because there aren't any).
2017-02-27 09:35:18 -05:00
ede7406b08
Merge branch 'master' into work
2017-02-08 15:17:01 -05:00
516d1c33fb
Update at Wed Feb 8 15:16:59 EST 2017 by tim
2017-02-08 15:16:59 -05:00
0ad5730701
Corrected an error where snprintf() was not used when printing
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formatted side-by-side output, causing a crash for names that
exceed the 40-column limit.
2017-02-08 15:16:24 -05:00
24d98ff0d3
Removed backup file for netgen.tcl.in, and made corrections for
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the output JSON format, which was incorrect when some entries
were empty.
2017-01-09 17:06:23 -05:00
092c99dc1b
Merge branch 'master' into work
2017-01-09 12:53:00 -05:00
4659b0795d
Update at Mon Jan 9 12:52:59 EST 2017 by tim
2017-01-09 12:52:59 -05:00
b1924bff65
Finished implementing the Tcl list output format, and added a
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routine to convert the list output format to a JSON output file,
for easy readback, parsing, and display using python.
2017-01-09 12:51:31 -05:00
bd356553fd
Merge branch 'master' into work
2017-01-07 06:57:27 -05:00
46458f2836
Update at Sat Jan 7 06:57:25 EST 2017 by tim
2017-01-07 06:57:25 -05:00
8deccaad9c
Fixed a bug in the combine routine that causes a segfault; added
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preliminary support for a Tcl list output format.
2017-01-07 06:56:51 -05:00
4f24915661
Correction to device property matching code to fix a problem that
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caused LVS(A, B) to give different results for property errors
than LVS(B, A).
2016-12-12 13:31:56 -05:00
fdab366627
Corrected typo with == vs. =
2016-12-12 11:51:24 -05:00
310d7512a0
Removed backup file.
2016-12-12 11:32:52 -05:00
86f52b164a
Merge branch 'master' into work
2016-12-12 11:32:44 -05:00
4a47c3076d
Update at Mon Dec 12 11:32:42 EST 2016 by tim
2016-12-12 11:32:42 -05:00
777498b30e
Completed the implementation of serial/parallel device network
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matching.
2016-12-12 11:32:07 -05:00
8300531858
Fixed an error that prevented 'circuit1' and 'circuit2' from being
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used in the general cell name format as advertised (in fact caused
a segfault), without which all setup file have to be very circuit-
specific.
2016-12-07 22:22:57 -05:00
80378d8816
Several errors in the serial combination code fixed, and then
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the serial combination routine was disabled so as not to post a
non-working version, since the parallel/serial property networks
are not analyzed. This should be completed soon.
2016-12-07 21:21:15 -05:00
80d981a672
Merge branch 'master' into work
2016-12-07 15:01:56 -05:00
809a3c16e9
Update at Wed Dec 7 15:01:55 EST 2016 by tim
2016-12-07 15:01:55 -05:00
8d976e5686
Added more handling of serial/parallel device networks, including
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making any subcircuit serializable by using the new command option
"property (device) serial|parallel enable|disable". Note that as
of this commit, serial device detection is enabled but serial
networks are not collapsed for matching, which will tend to lead
to property errors in serial devices until this code is added,
which should be in a day or two.
2016-12-07 14:57:43 -05:00
577dfb5a28
Merge branch 'master' into work
2016-11-11 09:52:19 -05:00
46252ad6b9
Update at Fri Nov 11 09:52:18 EST 2016 by tim
2016-11-11 09:52:18 -05:00
Tim Edwards
Tim Edwards