information for a non-matching pin in circuit1 and generates a
proxy pin in circuit2---there is some case where this is redundant,
I think, but I need to find the example.
saying that pins were mismatched when pin matching was never run
accidentally resulted in pin matching not being applied to black-box
entries. This has been corrected.
continues to allow missing pins to match unconnected pins, but
*only* on subcircuits below the top level. This essentially forces
layouts to separate merged pins with metal resistors, although
there should be an option in magic's ext2spice routine that allows
"equiv" statements, when declaring equivalence of two ports, to be
replaced by a zero volt source or zero ohm ideal resistor.
pins on non-black-boxed circuits as it does not black-boxed circuits,
but specifically looking for pins that are disconnected on both sides,
since those do not appear in the node list and are not otherwise
handled. Otherwise, disconnected pins will appear to have disappeared
from the first netlist.
a final parallel or series combination needs to be done but there
are still multiple property records. The multiplier was being
incorrectly applied twice, causing an automatic mismatch in
parameter values.
of multiple devices during flattening, that will skip over a node
record at the end of a subcircuit call being flattened and therefore
remove it from the netlist.
list that it prints in the side-by-side element mismatch comparison
for an element, when there is no node record associated with the pin
connection. This makes the output clearer.
swapped, so that if pin names are swapped on the top level, netgen will
report this as a final error message. Otherwise, the mismatch is only
reported back in the pin list where it is not obvious.
The algorithm is to run without exhaustive subdivision until the
last step because this is much faster. The final iteration must
be run with exhaustive subdivision on, or else it is possible to
have cells with swapped pins matching. The routines that resolve
automorphisms were setting exhaustive subdivision for the final
iteration. But simple "run converge" and "run resolve" were not.
add properties across multiple property records in the last matching
step, if there are still multiple properties and the values can be
combined. Previously, netgen had been assuming that there would only
be one property record left at this point, which is not true. This
shows up particularly for BSIM fingered devices, since "nf" is
ignored.
for file extensions is greedy and picks the first matching extension
starting at the front of the string, such that, e.g., "file.ext.spice"
is interpreted as a ".ext" file and not a ".spice" file.
run to the end of the list of circuit elements. Also corrected
another issue caused by the flag to denote multiple no-connect pins,
which can be on an instance pin and so cannot share the data from the
instance record.
device with one or more no-connect pins. The flag that indicates a
no-connect pin was checked incorrectly, potentially causing obscure
and misleading property mismatch messages to be generated.
records, which were being ignored. This really only applies to
parallel subcircuits being flattened. To flatten correctly requires
that any circuit with N property records must be flattened into the
parent at least N times. To do: Must look for M > 1 records in the
properties and flatten (M - 1) additional times.
unconnected pins in the other netlist are marked as "(no pin)"
rather than "(no matching pin)". This allows a script parsint the
JSON file (e.g., count_lvs.py from qflow) to distinguish between a
real pin error and one that can be ignored.
without netgen noticing---this behavior got broken by an
exception for "black box" circuits, but failed to check if the
circuit really was marked as a "black box" or not. Fixing that
revealed another issue with verilog implicit pins. Both issues
have now been corrected.
netgen. More work will be done later. Also: Removed the
derived file lvs_manager.py from the repository, and modified
the Makefile to remove it as part of "make clean".
other devices that do not have a "critical property" that determines
which properties can add together was flawed and messed up the sorting
of devices like transistors and resistors that do have a critical
property. Reworked the sorting order so that it makes sense for both
situations.
Also corrected a superficial issue with an attempt to print out an
instance name that doesn't exist. There is an underlying bug here
related to cells that have no pins and/or no contents which has not
been debugged. The fix just keeps netgen from segfaulting.
no pins at all. This overrides the default behavior of treating
empty cells as "black-box" entries, and avoids attempts to compare
cells like logo artwork.
different additive properties (like transistor width) to combine;
this is totally wrong and may have been left over from code written
before the routine was split into simple combinations (add similar
devices) and agressive combinations (e.g., add widths together).
Sai Charan Lanka
Tim Edwards