Commit Graph

671 Commits

Author SHA1 Message Date
Tim Edwards 224050f153 "ocd_git_pure automatic update to repo" 2019-10-09 03:00:08 -04:00
Tim Edwards 74e8c3e168 Merge branch 'master' into netgen-1.5 2019-10-09 03:00:08 -04:00
Tim Edwards f12d03fcff Corrected the verilog parser for handling parameters and parameters
with increment/decrement syntax at the end.  Also the parser now
handles additional keywords associated with behavioral verilog
(initial, specify) and flags modules with them as black-box entries.
2019-10-08 12:18:13 -04:00
Tim Edwards 95a29fcd8c "ocd_git_pure automatic update to repo" 2019-09-11 03:00:07 -04:00
Tim Edwards 723a950fd3 Merge branch 'master' into netgen-1.5 2019-09-11 03:00:07 -04:00
Tim Edwards f04c72b984 Corrected missing case (greater-than or equal instead of greater than)
that affects vectors sliced across instance arrays.  Can cause vector
numbers to be out-of-bounds if an instance is arrayed but each
instance is listed separately.
2019-09-10 10:52:15 -04:00
Tim Edwards e3368cb22a "ocd_git_pure automatic update to repo" 2019-09-10 03:00:08 -04:00
Tim Edwards f06e6548bb Merge branch 'master' into netgen-1.5 2019-09-10 03:00:08 -04:00
Tim Edwards d38bd77825 Additional fixes to the verilog parser, including handling the
inline-I/O syntax with "wire" (e.g., "input wire [3:0] test")
and addressed the failure to add buses declared in inline I/O
to the list of known buses.
2019-09-09 13:42:21 -04:00
Tim Edwards ea4083893c A fairly large refactoring of the conditional handling code in the
verilog parser.  The parser should now be able to handle any
conditionals anywhere in the verilog code.  Also a bug was found
in the code that handles "a = b" assignments, and corrected.
2019-09-09 11:26:31 -04:00
Tim Edwards 72ed19ff36 "ocd_git_pure automatic update to repo" 2019-09-09 03:00:10 -04:00
Tim Edwards 39b8e3d14a Merge branch 'master' into netgen-1.5 2019-09-09 03:00:10 -04:00
Tim Edwards 3dc70148d1 Added support in the verilog parser for definitions anywhere in the
code using the backtick expression.  Also expanded the parsing of
"ifdef", "ifndef", and "endif" to include "elsif" and "else".  All
forms of "if" statements should now be handled, since verilog does
not define boolean expressions in ifdef operators like most languages
do.
2019-09-08 19:59:27 -04:00
Tim Edwards b63dfa8638 "ocd_git_pure automatic update to repo" 2019-08-20 03:00:20 -04:00
Tim Edwards f918f33c51 Merge branch 'master' into netgen-1.5 2019-08-20 03:00:20 -04:00
Tim Edwards a8576d26a9 Modified the netgen token parser, which (unwisely) is used both for
SPICE and verilog, in spite of the syntactical differences, to
account for the trick that qflow uses to replace the trailing space
in a verilog backslash-escaped name with a second backslash to get
a SPICE-compatible name that can be easily converted back to its
original verilog name without loss of information.  What this means
is that verilog can read SPICE files containing verilog names (which
is illegal SPICE) and verilog files containing hacked-backslash
names (which is illegal verilog).  This should be mostly harmless
although the wisdom of it is surely questionable.
2019-08-19 17:06:05 -04:00
Tim Edwards 63b2e48ea1 "ocd_git_pure automatic update to repo" 2019-08-13 03:00:08 -04:00
Tim Edwards 6e63f49d53 Merge branch 'master' into netgen-1.5 2019-08-13 03:00:07 -04:00
Tim Edwards a31390f152 Some corrections and updates to the commit of a few days ago to
handle wire bundles in wire assignments and pin connections.
Also corrected an error in which a comment after a wire statement
causes parsing issues.
2019-08-12 13:58:19 -04:00
Tim Edwards 419b6de29a "ocd_git_pure automatic update to repo" 2019-08-11 03:00:07 -04:00
Tim Edwards 205cf2aa58 Merge branch 'master' into netgen-1.5 2019-08-11 03:00:07 -04:00
Tim Edwards 44ec952872 Expanded the verilog parser to handle most forms of allowable wire and
assignment statements in verilog netlists, including assignment of
signal bundles.  Also corrected handling of signal bundles in pin
connections, which had been corrected in qflow's verilog parser but
not copied back to netgen.  Note that the syntax for signals multiplied
N times is still not handled.
2019-08-10 22:30:57 -04:00
Tim Edwards 52b6766fc8 "ocd_git_pure automatic update to repo" 2019-08-04 03:00:20 -04:00
Tim Edwards 7b0bdd29e8 Merge branch 'master' into netgen-1.5 2019-08-04 03:00:20 -04:00
Roman-Parise 3892529873 Removed generated files and edited .gitignore 2019-08-03 16:27:13 -04:00
Roman-Parise e3b51c6004 Fixed configure scripts for FreeBSD builds 2019-08-03 16:24:24 -04:00
Roman-Parise 3200b1bf95 Added FreeBSD installation comment to README. 2019-08-03 16:24:24 -04:00
Tim Edwards 814652e552 Updated tkcon.tcl, which was not corrected for a minor problem that
affects use with Tcl/Tk 8.6 (text option "-under" not recognized;
must be "-underline").
2019-08-03 16:22:26 -04:00
Tim Edwards 433cbd090a "ocd_git_pure automatic update to repo" 2019-07-25 03:00:16 -04:00
Tim Edwards 3087bd3337 Merge branch 'master' into netgen-1.5 2019-07-25 03:00:16 -04:00
Tim Edwards 4d138b64ca Corrected a missing "#ifdef TCL_NETGEN" around a Tcl subroutine
call, in objlist.c.
2019-07-24 11:13:25 -04:00
Tim Edwards b79a29d662 "ocd_git_pure automatic update to repo" 2019-07-15 03:00:27 -04:00
Tim Edwards bf9c61e412 Merge branch 'master' into netgen-1.5 2019-07-15 03:00:27 -04:00
Tim Edwards 9a2902abbb Removed "makedbh", which was copied from Magic (a long, long time
ago) when building out the netgen Makefile, and never removed.  The
script is very specific to Magic.
2019-07-14 09:39:39 -04:00
Tim Edwards 8d34bd372d "ocd_git_pure automatic update to repo" 2019-07-03 03:00:22 -04:00
Tim Edwards 229c2931a8 Merge branch 'master' into netgen-1.5 2019-07-03 03:00:22 -04:00
Tim Edwards 840f997133 Corrected a typo that somehow crept into the verilog delimiter set,
replacing the semicolon with a colon, which basically hoses the
verilog parser.
2019-07-02 10:45:10 -04:00
Tim Edwards b8da97deb1 "ocd_git_pure automatic update to repo" 2019-06-16 03:00:15 -04:00
Tim Edwards b7187d5899 Merge branch 'master' into netgen-1.5 2019-06-16 03:00:15 -04:00
Tim Edwards cb3cf592e8 Corrected the arguments to the configure script from the top-level
wrapper.
2019-06-15 12:43:13 -04:00
Tim Edwards b1d40e6d12 Corrected an error in the "permute forget" Tcl command option that
would attempt to access uninitialized variables, possibly causing
a crash.
2019-06-15 12:29:08 -04:00
Tim Edwards edbefbd1c4 Corrected an error in handling partial buses connected to a
full-bus pin in a module instance.
2019-06-15 03:05:50 -04:00
Tim Edwards d27d441c58 "ocd_git_pure automatic update to repo" 2019-06-13 03:00:05 -04:00
Tim Edwards 48c9e6b292 Merge branch 'master' into netgen-1.5 2019-06-13 03:00:05 -04:00
Tim Edwards 527cdb3dab Corrected error in detecting S and M. 2019-06-12 11:11:28 -04:00
Tim Edwards ced5846da3 "ocd_git_pure automatic update to repo" 2019-05-18 03:00:05 -04:00
Tim Edwards b99d33064f Merge branch 'master' into netgen-1.5 2019-05-18 03:00:04 -04:00
Tim Edwards ee66c00121 Further refined the last commit based on the change in definition of
a "critical property".  This lets a device define multiple critical
properties, all of which must match before additive properties can
be combined in the same device.
2019-05-17 14:33:26 -04:00
Tim Edwards f40a50d3b8 Corrected property value merging (again). By the rules of the
re-worked property command, "critical" properties must match
across devices so that all other properties can be combined as
specified (addition, parallel combination, or none).  The code was
still based on the older notion of the "critical" property being
the one to add (and thus preventing multiple properties from being
added in different ways).  This has now been fixed.
2019-05-17 11:25:34 -04:00
Tim Edwards 399472e940 "ocd_git_pure automatic update to repo" 2019-05-07 09:13:00 -04:00