be reported at the end if there was a port error. This is important
because port errors often resolve themselves, but the cell should not
be reported clean if the port errors resolved but it had property
errors. Also: Added a method to derive area and/or perimeter
properties from length and width, so that capacitors can be combined
in parallel without regard to which dimension is width and which is
length. This feature has only been lightly tested.
a spice netlist falls exactly on the last non-null position of the
input buffer after the buffer has been expanded to accept more
input data, then the next line gets read in automatically, and
the newline gets treated as whitespace and not a newline.
is created without setting the cell name or instance name. That
can cause a crash condition when attempting to locate the instance
from the net record.
to strdtok() can differentiate between reading verilog and reading
SPICE. Otherwise, SPICE containing the (dubious) syntax of using
backslashes in names will get treated as a verilog name with
verilog backslash notation, with generally undesirable results.
When called from the SPICE reading routine, backslashes are
treated as-is and not as verilog notation.
expression in a property that was not necessarily a parameter,
and if it wasn't, then netgen would crash. Surfaced by an
example using complicated parameters that netgen was apparently
unable to handle (an issue for another day; the main goal here
was to avoid a segmentation violation).
tracker #96) in which a subcircuit with only one port (in this
case, a pad) but which has properties (in this case, "M") will
fail to set the pointer position ahead of the property because
the loop starts after the first pin, so it has already missed
the position that needs to be saved. Fixed by initializing
the value to the first pin position before starting the loop.
to be caused by failing to have a systematic way of determining
which pin's hash value would be used for the hash value of all the
pins. Because equivalent cells in the two netlists may have pins in
different order, it was possible that they might end up with
different hashes. This was solved simply by always taking the
larger hash value of the two pins belonging to the permutable pair.
Now permutation works correctly for arbitrary subcircuits.
(Previously it worked for low-level components like MOSFETs because
the pin order is always the same.)
forced flattening to be done whenever any pin mismatch occurred,
which undermined the whole proxy pin method. With the proxy pins
fixed, reinstated the method of avoiding flattening when pin
issues can be trivially corrected. Also: Added output to the
pin matching for one mismatch case that was being missed.
decided that it is beneficial to break symmetries by net name;
it's just that net names should not be used before all symmetries
related to pins have been broken. So I rewrote the compare
routine to take an argument allowing or disallowing net name
matches, and make one call to break symmetries by pin name
followed by another call to break symmetries by net name. This
still solves the original problem, but does not allow symmetries
to be broken randomly on internal nets if names have been matched
in both netlists. Otherwise the output may report nets that
appear to be swapped, making the output confusing.
to check that the nodes with matching names are pins, but never does.
This results in an attempt to resolve automorphs by matching pin
names AND net names. However, net names can match without the nets
matching, as pointed out by Andrey Bondar (private communication).
Fixed simply by adding the specified check that the node being name-
matched is actually a pin.
open-source-silicon slack on Nov. 3 in which the simple verilog
expression "assign name1 = name2[a:b]"; this revealed an error
where the parsing of "name2" was being incorrectly run with
GetBusTok() which must be called when the token starts with "[".
This problem existed both for the left-hand-side parsing and
the right-hand-side parsing, and has been fixed for both (where
either side may be a subset of a bus and the other a complete
bus).
a verilog escaped string against an equivalent non-escaped
string (requires that the escaped string differs from the non-
escaped string by having a "\" at the front and " " at the end.
The space character is always maintained as part of the string).
formatted output to make it much cleaner and easier to read. This
is in preparation of correcting the circuit1<-->circuit2 asymmetry
in the MatchPins() routine.
the critical property (e.g., L for transistors) is required to
match exactly between devices in order to allow the additive
property (e.g., W for transistors) to be summed. The critical
property should match if all values are within the slop value,
for floating-point values. Note: The implementation is still
not rigorous, as the saved critical value may shift from
device to device; so comparing, e.g., 1.00 to 1.01 to 1.02 to
1.03, etc., can find that all individual comparisons are within
the slop value even though the slop is exceeded across all values.
ditch effort of matching based on combining devices with the same
critical property (e.g., adding gate widths together for transistors
of the same gate length, if the property records remain stubbornly
mismatched to the end). Thanks to Bondar Andrey Renatovich for
surfacing this issue and providing a reproducible example.
a long time ago into the code. The improvements collided with
intervening changes to the same routines and would not merge
cleanly, which is why they were never merged. Step 1: Show the
net name of a matching net that is missing a pin. Remove output
of missing pins that is redundant (pin names being output twice).
instance is matched to a verilog module definition, and the SPICE
instance is read before the verilog definition, forcing a
placeholder cell to be created. Netgen will now make the
assumption that the verilog ports are in the same order as the
SPICE instance port order. At the same time, it will output a
warning message that it is making this not-necessarily-warranted
assumption. If the number of ports don't match or the placeholder
did not come from a SPICE instance, then the placeholder pins are
left alone.
some errors failing to list in the output while also being responsible
for a number of non-errors showing up in the output. This fix may
substantially clean up netgen output. Also: Added text to the
output noting that pin matching may be incorrect with respect to
symmetries if the nets have failed to match.
port-to-port short (formed by "assign" in verilog or zero-valued
resistors in SPICE) does not get checked when counting nodes
before adding a proxy pin to a subcircuit in that cell, causing
the proxy pin to be assigned the same node number and forming an
unintended connection to the port-to-port connecting net.
such a zero-ohm resistors or zero-volt sources during the pre-match
phase, since the list of nodes gets changed by merging nets across
the removed devices. Otherwise, the node-name cache gets
corrupted and random LVS errors occur.
structure variable is not checked for the condition of being NULL
before attempting to read a component of the structure. These
conditions imply that something is badly wrong in the netlist but
should not be causing a segfault.
pass the right cell name to the routine which counts the number of
pins. Using this in a setup file will prevent netgen from spending
time matching low-level devices.
Tim Edwards