the parallel sorting routine. This fixes occasional property
errors with series-connected devices such as resistors. (2) Added
a method to associate properties with specific pins when pins are
permutable. This allows netgen to properly check a value like
source/drain area when the definition of source and drain has
changed due to permutation of the device. (3) Added a "property"
command extension "associate" to associate a property with a pin,
for use with the method described in (2).
LVS result. The property matching was failing to match (M=1) to
(M!=1) if M was not registered as a property name (which it often
isn't). This would allow devices with different numbers of
instances in parallel to be put in the same matching group,
which then could later identify as a mismatch if the instances
were checked in a different order.
netgen is supposed to be checking properties for symmetry sorting,
but not reporting anything. This causes mysterious property
mismatch errors that don't actually exist to show up in the
output.
underlying issue (which needs to be investigated), but it does
prevent netgen from crashing when it encounters it (netgen will
generate an erro message instead).
significant overhaul of the MatchPins() code, and better handles
issues with pins disconnected from nets and removes cases in
which proxy pins are incorrectly generated.
request #59 ("Pin match"). Because the pull request has rather
sweeping modifications, I am doing this in two steps. The change
that most breaks with existing comparison methods is in the
PinMatch() routine in netcmp.c, where the method of generating
proxy pins has been removed. There are specific cases for which
the proxy pin method exists, although these were coping with
issues arising from extraction in magic which have been dealt
with to some extend. Possibly the proxy pin method is no longer
needed. So the PinMatch() changes will be done in a second
commit where it's easier to revert or modify the changes without
affecting the modifications from this commit.
were implicit in the first instances but made explicit in a later
one. If more than one such implicit pin was handled for the same
cell, then the pin count would become wrong and rather unpredictable
behavior results.
to a single net (as can be done with assignments in verilog or with
zero-voltage sources or zero-value resistors in SPICE). Corrected
an error in the SPICE netlist reader that prevented the proper use
of zero-voltage sources as net splitters.
delimiter set when parsing pin names (the correct delimiter set
was used in one place but not in another). Extended the pin
matching to include the minor hack of ignoring the backslash
before backslash-escaped verilog names when there is otherwise
no exact match, since many tools convert verilog to SPICE by
removing the backslash and trailing space. This avoids pin
mismatches in a known set of use cases.
by Anton Blanchard, which prevents the double-loop in the
PropertyOptimize() routine from continuing the outer loop if
all devices in the run have already been merged.
summary, so that the summary lists the total number of devices as well
as the number of devices after parallel optimization, in the form
"device_name (M->N)", where "M" is the total number of devices, and
"N" is the number of devices after parallel combination. This makes
the output somewhat more meaningful to the end user. Implementation
as discussed in github issue #47.
should not be called after CreateTwoLists(). CreateTwoLists()
was being called in one case only to print the contents of the
cells, so that part was pulled out into a separate routine.
for each connection in the dump of incorrect nets. This is
definitely critical to finding local swapping errors, and needs
to be incorporated into the non-debug mode, preferably as part of
the JSON file dump. But that's for later.
contents (previously wasn't done), and also added sorting for items with
non-matching names which have only one item in the group for each circuit
(so they must be matching in some sense). This makes the output a bit
more readable without re-enabling the compute-intensive sorting method
for non-matching entries.
This fixes crash on macos due to wrong hash() being linked in.
It also makes sure that proper function defs are declared and available
(as required by C99) to make compile possible in newer compilers (e.g.
Apple clang) and to some extend prevent similar linkage issues happening
again.
Changed line breaks in log and stdout to better differentiate subcircuits.
Added merged series device counts and differentiated from parallel merged device counts.
Added file number to disconnected net, merged count messages.
Changed black box errors to show file numbers instead of hard coded values.
Final error cell list changed from all on one line to one per line.
Removed redundant display in black box warning.
information for a non-matching pin in circuit1 and generates a
proxy pin in circuit2---there is some case where this is redundant,
I think, but I need to find the example.
continues to allow missing pins to match unconnected pins, but
*only* on subcircuits below the top level. This essentially forces
layouts to separate merged pins with metal resistors, although
there should be an option in magic's ext2spice routine that allows
"equiv" statements, when declaring equivalence of two ports, to be
replaced by a zero volt source or zero ohm ideal resistor.
pins on non-black-boxed circuits as it does not black-boxed circuits,
but specifically looking for pins that are disconnected on both sides,
since those do not appear in the node list and are not otherwise
handled. Otherwise, disconnected pins will appear to have disappeared
from the first netlist.
a final parallel or series combination needs to be done but there
are still multiple property records. The multiplier was being
incorrectly applied twice, causing an automatic mismatch in
parameter values.
of multiple devices during flattening, that will skip over a node
record at the end of a subcircuit call being flattened and therefore
remove it from the netlist.
list that it prints in the side-by-side element mismatch comparison
for an element, when there is no node record associated with the pin
connection. This makes the output clearer.
swapped, so that if pin names are swapped on the top level, netgen will
report this as a final error message. Otherwise, the mismatch is only
reported back in the pin list where it is not obvious.
add properties across multiple property records in the last matching
step, if there are still multiple properties and the values can be
combined. Previously, netgen had been assuming that there would only
be one property record left at this point, which is not true. This
shows up particularly for BSIM fingered devices, since "nf" is
ignored.
run to the end of the list of circuit elements. Also corrected
another issue caused by the flag to denote multiple no-connect pins,
which can be on an instance pin and so cannot share the data from the
instance record.
device with one or more no-connect pins. The flag that indicates a
no-connect pin was checked incorrectly, potentially causing obscure
and misleading property mismatch messages to be generated.
unconnected pins in the other netlist are marked as "(no pin)"
rather than "(no matching pin)". This allows a script parsint the
JSON file (e.g., count_lvs.py from qflow) to distinguish between a
real pin error and one that can be ignored.
without netgen noticing---this behavior got broken by an
exception for "black box" circuits, but failed to check if the
circuit really was marked as a "black box" or not. Fixing that
revealed another issue with verilog implicit pins. Both issues
have now been corrected.
other devices that do not have a "critical property" that determines
which properties can add together was flawed and messed up the sorting
of devices like transistors and resistors that do have a critical
property. Reworked the sorting order so that it makes sense for both
situations.
Also corrected a superficial issue with an attempt to print out an
instance name that doesn't exist. There is an underlying bug here
related to cells that have no pins and/or no contents which has not
been debugged. The fix just keeps netgen from segfaulting.
different additive properties (like transistor width) to combine;
this is totally wrong and may have been left over from code written
before the routine was split into simple combinations (add similar
devices) and agressive combinations (e.g., add widths together).
class during setup, for the purpose of generating some derived
value that is used for merging and sorting, such as area = l*w.
Note that this likely needs adjusting so that the expression is
evaluated but not replaced for the purpose of sorting, since the
values to the parameter may change after parallel and series
merging.
cause inexplicable output in case of a property error by showing a
netlist topography error instead of a property error (but the output
shows that the netlists match, and there is no reporting of any
property errors). This error was discovered while implementing a
better sorting method for parallel combination. The improved method
sorts on two properties rather than one, and so should not fall into
the error where, say, devices are sorted on W but have different L
for a device like a capacitor where no "critical" property is
specified (and other similar cases, although that is a common one).
Tim Edwards
D. Mitch Bailey
Kamyar Mohajerani