From c27d933adc2b790af9642169f602dfdd7a751da1 Mon Sep 17 00:00:00 2001 From: Tim Edwards Date: Fri, 1 Sep 2023 09:04:44 -0400 Subject: [PATCH] Modified some of the verilog read-in code to avoid a segmentation fault that would happen if the verilog had illegal syntax of a misspelled net name (although normally netgen is expected not to have to check the verilog for syntax, and there are probably many such cases of netgen failing to handle incorrect verilog and then crashing as a result). --- VERSION | 2 +- base/verilog.c | 13 +++++++++++-- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/VERSION b/VERSION index 47d3fe3..b05db56 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -1.5.256 +1.5.257 diff --git a/base/verilog.c b/base/verilog.c index 9ba310c..f74d7ff 100644 --- a/base/verilog.c +++ b/base/verilog.c @@ -1898,12 +1898,21 @@ skip_endmodule: if (i != -1) snprintf(nodename, MAX_STR_LEN, "%s[%d]", noderoot, i); - else + else if (lhs != NULL) strncpy(nodename, lhs->name, MAX_STR_LEN - 1); + else { + Printf("Error: Improper node name \"%s\".\n", noderoot); + goto skip_endmodule; + } if (j != -1) snprintf(assignname, MAX_STR_LEN, "%s[%d]", assignroot, j); - else + else if (rhs != NULL) strncpy(assignname, rhs->name, MAX_STR_LEN - 1); + else { + Printf("Error: Improper assignment name \"%s\".\n", + assignroot); + goto skip_endmodule; + } join(nodename, assignname);