From b5432d139bb58a87c9fb642ffcd1ef550a269766 Mon Sep 17 00:00:00 2001
From: "R. Timothy Edwards" <tim@opencircuitdesign.com>
Date: Thu, 9 Oct 2025 10:36:41 -0400
Subject: [PATCH] Corrected a corner-case where a module with no ports in
 verilog was creating an implicit net for the stand-in "(no pins)" port.

---
 VERSION        |  2 +-
 base/verilog.c | 12 +++++++-----
 2 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/VERSION b/VERSION
index 29a5a3d..cf5e6f2 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-1.5.302
+1.5.303
diff --git a/base/verilog.c b/base/verilog.c
index 548d274..4e405e9 100644
--- a/base/verilog.c
+++ b/base/verilog.c
@@ -2614,13 +2614,15 @@ nextinst:
 	       if (scan == NULL) {
 		  char localnet[MAX_STR_LEN];
 
-		  /* Assume an implicit unconnected pin */
-		  sprintf(localnet, "_noconnect_%d_", localcount++);
-		  Node(localnet);
-		  join(localnet, obptr->name);
-		  Fprintf(stdout,
+		  /* Assume an implicit unconnected pin, unless there are no pins */
+		  if (strcmp(obpinname, "(no pins)")) {
+		     sprintf(localnet, "_noconnect_%d_", localcount++);
+		     Node(localnet);
+		     join(localnet, obptr->name);
+		     Fprintf(stdout,
 			 "Note:  Implicit pin %s in instance %s of %s in cell %s\n",
 			 obpinname, locinst, modulename, CurrentCell->name);
+		  }
 	       }
 	       else if (GetBus(scan->net, &wb) == 0) {
 		   char *bptr2;