This website requires JavaScript.
Explore
Help
Register
Sign In
luke
/
netgen
mirror of
https://github.com/RTimothyEdwards/netgen.git
Watch
1
Star
0
Fork
You've already forked netgen
0
Code
Issues
Packages
Projects
Releases
Wiki
Activity
c7fa0324d9
netgen
/
VERSION
2 lines
8 B
Plaintext
Raw
Normal View
History
Unescape
Escape
Added a piece of code that handles implicit pins in verilog by doing the following: (1) Checking that the parent cell is verilog, (2) only running after the two cells themselves have been compared and matched, then (3) added the missing pin or pins while reordering pins on instances (note: this may not work if the verilog netlist is the first passed to netgen; that case needs to be checked).
2024-02-02 20:51:10 +01:00
1.5.266