121 lines
3.6 KiB
Python
121 lines
3.6 KiB
Python
from amaranth.sim import Simulator
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from manta.uart import RecieveBridge
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from manta.utils import *
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bridge_rx = RecieveBridge()
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def verify_read_decoding(bytes, addr):
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"""
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Send a series of bytes to the receive bridge, and verify that the bridge places
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a read request with the appropriate address on the internal bus.
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"""
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valid_asserted = False
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yield bridge_rx.valid_i.eq(1)
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for i, byte in enumerate(bytes):
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yield bridge_rx.data_i.eq(byte)
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if (yield bridge_rx.valid_o) and (i > 0):
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valid_asserted = True
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if (yield bridge_rx.addr_o) != addr:
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raise ValueError("wrong addr!")
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if (yield bridge_rx.rw_o) != 0:
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raise ValueError("wrong rw!")
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if (yield bridge_rx.data_o) != 0:
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raise ValueError("wrong data!")
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yield
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yield bridge_rx.valid_i.eq(0)
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yield bridge_rx.data_i.eq(0)
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if not valid_asserted and not (yield bridge_rx.valid_o):
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raise ValueError("Bridge failed to output valid message.")
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def verify_write_decoding(bytes, addr, data):
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"""
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Send a series of bytes to the receive bridge, and verify that the bridge places
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a write request with the appropriate address and data on the internal bus.
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"""
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valid_asserted = False
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yield bridge_rx.valid_i.eq(1)
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for i, byte in enumerate(bytes):
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yield bridge_rx.data_i.eq(byte)
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if (yield bridge_rx.valid_o) and (i > 0):
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valid_asserted = True
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if (yield bridge_rx.addr_o) != addr:
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raise ValueError("wrong addr!")
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if (yield bridge_rx.rw_o) != 1:
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raise ValueError("wrong rw!")
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if (yield bridge_rx.data_o) != data:
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raise ValueError("wrong data!")
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yield
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yield bridge_rx.valid_i.eq(0)
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yield bridge_rx.data_i.eq(0)
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if not valid_asserted and not (yield bridge_rx.valid_o):
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raise ValueError("Bridge failed to output valid message.")
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def verify_bad_bytes(bytes):
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"""
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Send a series of bytes to the receive bridge, and verify that the bridge does not
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place any transaction on the internal bus.
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"""
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yield bridge_rx.valid_i.eq(1)
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for byte in bytes:
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yield bridge_rx.data_i.eq(byte)
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if (yield bridge_rx.valid_o):
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raise ValueError("Bridge decoded invalid message.")
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yield
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yield bridge_rx.valid_i.eq(0)
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def test_read_decode():
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def testbench():
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yield from verify_read_decoding(b"R0000\r\n", 0x0000)
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yield from verify_read_decoding(b"R1234\r\n", 0x1234)
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yield from verify_read_decoding(b"RBABE\r\n", 0xBABE)
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yield from verify_read_decoding(b"R5678\n", 0x5678)
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yield from verify_read_decoding(b"R9ABC\r", 0x9ABC)
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simulate(bridge_rx, testbench)
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def test_write_decode():
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def testbench():
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yield from verify_write_decoding(b"W12345678\r\n", 0x1234, 0x5678)
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yield from verify_write_decoding(b"WDEADBEEF\r\n", 0xDEAD, 0xBEEF)
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yield from verify_write_decoding(b"WDEADBEEF\r", 0xDEAD, 0xBEEF)
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yield from verify_write_decoding(b"WB0BACAFE\n", 0xB0BA, 0xCAFE)
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simulate(bridge_rx, testbench)
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def test_no_decode():
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def testbench():
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yield from verify_bad_bytes(b"RABC\r\n")
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yield from verify_bad_bytes(b"R12345\r\n")
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yield from verify_bad_bytes(b"M\r\n")
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yield from verify_bad_bytes(b"W123456789101112131415161718191201222\r\n")
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yield from verify_bad_bytes(b"RABCG\r\n")
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yield from verify_bad_bytes(b"WABC[]()##*@\r\n")
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yield from verify_bad_bytes(b"R\r\n")
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simulate(bridge_rx, testbench)
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