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manta/examples/verilog/nexys4_ddr/uart_logic_analyzer
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Fischer Moseley f91f7c5fbb meta: add pre-commit, commit changes it makes 2024-11-27 19:10:52 -07:00
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.gitignore meta: add pre-commit, commit changes it makes 2024-11-27 19:10:52 -07:00
build.sh meta: add pre-commit, commit changes it makes 2024-11-27 19:10:52 -07:00
build.tcl rename Nexys A7 to Nexys 4 DDR 2024-05-12 10:35:18 -07:00
manta.yaml meta: add pre-commit, commit changes it makes 2024-11-27 19:10:52 -07:00
top_level.sv meta: add pre-commit, commit changes it makes 2024-11-27 19:10:52 -07:00
top_level.xdc meta: add pre-commit, commit changes it makes 2024-11-27 19:10:52 -07:00