39 lines
2.5 KiB
Markdown
39 lines
2.5 KiB
Markdown
## IO Core
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- add interface read/write to python
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- test examples that build
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- update IO core read/write memory handling to be less ugly
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- add logic for ports >16 bits in width
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- figure out what happens for module naming - it's possible we could have two modules that have the same ports but have different names
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- do we say that port names have to be globally unique? or do we allow something like `module_name_module_type_inst` for example
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## Logic Analyzer Core
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- need to finish up simulations, those might get broken out into separate testbenches for each module
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- need to write tests - this will be hard because there's no template to go off of, so need to autogenerate before running tests
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## BRAM Core
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- write HDL
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- write tests
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- write interface
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## Python API
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- find a better way of handling tabs
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- make finding a serial port possible even if no cores are configured
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- make autodetecting and automatically selecting a serial device possible
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- if we see a FT2232 on the device we should grab it
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## Documentation
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- Move stuff out of readme.md and into the docs front page - right now information is duplicated
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- Write out what technologies are being used here (iverilog for sim, gtkwave for vcd, makefile for simulation/lint/pushing to pypi, github actions for automated test and building the doc site, python for autogeneration, verilator for lint. for docs, mkdoc-material for the site, wavedrom for timing diagrams and draw.io for block diagrams)
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- Write out where stuff is being stored - `test/` contains all the systemverilog testbenches, `src/manta` contains all verilog and python needed to generate and run the cores, `doc/` contains the documentation site source files, `.github/` contains the github actions config, `examples/` is exactly what it sounds like
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- Write out the anatomy of manta.v and how `Manta` generates that
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- Write out what methods need to be implemented for Manta.generate_hdl() to actually be able to pick up on the cores
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- Write out what bus transactions look like and how messages get passed. probably going to need wavedrom for this.
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## Testing
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- need to add tests for the python itself - does it recognize bad yaml files and produce the right errors when trying to build from them? are good manta files synthesizeable?
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- try doing literally anything on Windows lol
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## Meta
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- probably want to make all the manta source pass verilator lint - doesn't look like this would be too hard to do
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- maybe install local github actions runner to ubuntu/macos/linux VM with boards attached to it or something - just to make sure that examples actually work for real |