Fischer Moseley db81d8cbf0 meta: replace Signal(1) with Signal()		2026-03-17 11:23:01 -06:00
..
ethernet_io_core.py	examples: fix #37, use proper indexing in Amaranth examples	2025-04-06 20:15:08 -06:00
uart_io_core.py	examples: fix #37, use proper indexing in Amaranth examples	2025-04-06 20:15:08 -06:00
uart_logic_analyzer.py	meta: replace Signal(1) with Signal()	2026-03-17 11:23:01 -06:00
uart_memory_core.py	examples: fix typos	2024-11-07 09:50:55 -07:00