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manta/examples/verilog/nexys4_ddr
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Fischer Moseley 13bc196a34 rename Nexys A7 to Nexys 4 DDR 2024-05-12 10:35:18 -07:00
..
ether_logic_analyzer_io_core rename Nexys A7 to Nexys 4 DDR 2024-05-12 10:35:18 -07:00
uart_host_to_fpga_mem rename Nexys A7 to Nexys 4 DDR 2024-05-12 10:35:18 -07:00
uart_io_core rename Nexys A7 to Nexys 4 DDR 2024-05-12 10:35:18 -07:00
uart_logic_analyzer rename Nexys A7 to Nexys 4 DDR 2024-05-12 10:35:18 -07:00