653 B

Raw Blame History

Roadmap

Prior to v1.0.0 release:

targeting August 2023

Clean up UART testbenches, make them actually test things
Pull text from thesis into documentation site
Update docs with API reference
Make super super sure everything works (need hardware for that)
Port logic analyzer examples to the icestick
IO Core: Clock domain crossing, check that >16 bit probes work
Logic Analyzer Core: CDC, trigger modes, external trigger

Prior to v1.1.0 release:

Fix Ethernet packet format
Switch from Scapy to Python sockets library

Prior to v1.2.0 release:

FuseSoC Integration