65 lines
3.5 KiB
Markdown
65 lines
3.5 KiB
Markdown
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Regardless of if you use Manta in a traditional Verilog-based workflow or natively in an Amaranth design, the general concept of operation is as follows:
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- Specify and configure the cores you wish to include in your FPGA design.
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- Generate RTL for these cores, and include this RTL in your design.
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- Build the design, and upload it to your device.
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- Operate the cores from the host machine.
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Manta’s cores are small, configurable blocks that each provide some functionality. More information on each core can be found on their respective documentation pages. Manta supports an arbitrary amount of unique cores, limited only by the available resources of your device.
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## Usage in Traditional Verilog-Based Workflows
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Although modern HDLs are rising in popularity, most existing FPGA designs use a Verilog-based workflow. This consists of synthesizing a number of Verilog files into a single design. Manta can easily be used in such a workflow, as described below:
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- The cores and interface used to communicate with them is specified in a configuration file, written in YAML. This file is typically named `manta.yaml` .
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- A Verilog file containing the cores specified in the configuration file is generated. This is most often done at the command line with the `manta gen` command (for example, `manta gen manta.yaml manta.v`) but can also be done with the `generate_verilog`method of the `Manta` Python class. This file contains the definition of a Verilog module named `manta`, which includes all the cores specified in the configuration file.
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- This `manta` module is instantiated in your design, and the signals to each core are connected to your logic. Connections are also made to the signals of the interface specified in the configuration file. The `manta inst` command can also be used to generate a Verilog instantiation that can be copy-pasted into your source.
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- After the design is built and uploaded to the FPGA, the cores are operated from the host machine. Each core exposes a Python API containing methods that can be invoked from a Python script. These are described in great detail in the documentation for each core.
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!!! success "VHDL works too!"
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If your FPGA design is VHDL-based, fret not! Most synthesis tools support mixed-language projects, and will happily ingest both a Verilog-based Manta module inside of a VHDL-based design. Just take care to ensure that the interfaces match.
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### Example
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A minimal example of a `manta.yaml` file may be observed below:
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```yaml
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cores:
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my_io_core:
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type: io
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inputs:
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my_input_signal: 6
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outputs:
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my_output_signal: 12
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uart:
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port: "auto"
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baudrate: 3e6
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clock_freq: 100e6
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```
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This includes a single IO core in the `manta` module, which communicates with the host machine over a 3Mbaud UART link. Instantiating this core in your design might look like the following, as generated by `manta inst`:
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```verilog
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manta manta_inst (
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.clk(clk),
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.rst(rst),
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.rx(rx),
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.tx(tx),
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.my_input_signal(my_input_signal),
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.my_output_signal(my_output_signal));
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```
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!!! note "Reset is active high!"
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The Manta instance will reset while `rst` is held high. If you want to share reset logic with an active low reset signal (for example, `rst_n`), be sure to invert it first.
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More examples of Verilog-based designs can be found in the [examples/verilog](https://github.com/fischermoseley/manta/tree/main/examples/verilog) folder of the repo.
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## Usage in Amaranth Designs
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Manta is written in Python, which allows it to easily export a native Amaranth API. |