41 lines
1.3 KiB
Markdown
41 lines
1.3 KiB
Markdown
# ToDo
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# Deadlines
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- _04/12_ - BRAM Core
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- _04/13_ - Logic Analyzer working with >16 bit inputs. Currently held up by the sample memory, but will be resolved once BRAM core is ruggedized.
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- _04/14_ - CDC in the Logic Analyzer. Should be handled automatically, but just need to test it - probably with a SD card example.
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- _04/15_ - _fischer's day off_
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- _04/16_ - VCD export and .mem export for hardware-in-the-loop
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__release to PyPI lists - manta v0.0.1 out__
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- _04/17_ - write logic analyzer lab
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- _04/18_ - beta tester round 2, run logic analyzer lab. ethernet tx if there's time
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- _04/19_ - Ethernet TX
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- _04/20_ - Ethernet TX
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- _04/21_ - Ethernet TX
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- _04/22_ - _fischer's day off_
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- _04/23_ - _fischer's day off_
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- _04/28/23_ - start writing docs site, move appropriate bits into thesis
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- _05/05/23_ - slack week
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- _05/12/23_ - thesis due
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- _05/19/23_ - thesis actually due
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## IO Core
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- clock domain crossing
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- add logic for ports >16 bits in width
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## Logic Analyzer Core
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- clock domain crossing
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- trigger modes
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- external trigger
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## Meta
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- consider making manta pass verilator lint - or at least as much of it as possible
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- [opencores](https://opencores.org/projects) listing
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- [fusesoc](https://github.com/fusesoc/fusesoc.github.io)
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- port more examples to the icestorm FPGA
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- hardware-in-the-loop testing? |