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manta/examples/verilog/nexys4_ddr
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Fischer Moseley 8f45546b5a manta: fix code generation from config file, update tests 2024-10-08 11:42:10 -06:00
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ether_logic_analyzer_io_core manta: fix code generation from config file, update tests 2024-10-08 11:42:10 -06:00
uart_host_to_fpga_mem manta: fix code generation from config file, update tests 2024-10-08 11:42:10 -06:00
uart_io_core manta: fix code generation from config file, update tests 2024-10-08 11:42:10 -06:00
uart_logic_analyzer rename Nexys A7 to Nexys 4 DDR 2024-05-12 10:35:18 -07:00