Fischer Moseley 1e5a247cf4 meta: set ruff max line length to 100 characters ... This should hopefully make the Amaranth source more readable, since indentation and the `m.d.sync +=` prefix take a bit of line space.		2026-02-25 13:18:23 -07:00
..
test_bridge_rx_sim.py	meta: sort imports with ruff	2024-10-08 11:42:10 -06:00
test_bridge_tx_sim.py	meta: sort imports with ruff	2024-10-08 11:42:10 -06:00
test_config_export.py	meta: set ruff max line length to 100 characters	2026-02-25 13:18:23 -07:00
test_ethernet_interface.py	ethernet: add individual methods for each flavor of MII	2024-11-27 19:10:52 -07:00
test_examples_build.py	meta: set ruff max line length to 100 characters	2026-02-25 13:18:23 -07:00
test_io_core_hw.py	meta: set ruff max line length to 100 characters	2026-02-25 13:18:23 -07:00
test_io_core_sim.py	docs: autogenerate Python API docs, update IO core docs	2024-10-08 11:42:10 -06:00
test_logic_analyzer_fsm_sim.py	tests: refactor to use Amaranth-native API	2024-10-08 11:42:10 -06:00
test_logic_analyzer_hw.py	meta: set ruff max line length to 100 characters	2026-02-25 13:18:23 -07:00
test_logic_analyzer_sim.py	docs: autogenerate Python API docs, update IO core docs	2024-10-08 11:42:10 -06:00
test_mem_core_hw.py	ethernet: add HWITL ethernet test	2024-11-27 19:10:52 -07:00
test_mem_core_sim.py	meta: set ruff max line length to 100 characters	2026-02-25 13:18:23 -07:00
test_source_bridge_sim.py	meta: sort imports with ruff	2024-10-08 11:42:10 -06:00
test_uart_baud_mismatch.py	meta: set ruff max line length to 100 characters	2026-02-25 13:18:23 -07:00
test_uart_rx_sim.py	meta: sort imports with ruff	2024-10-08 11:42:10 -06:00
test_uart_tx_sim.py	meta: sort imports with ruff	2024-10-08 11:42:10 -06:00
test_verilog_gen.py	meta: sort imports with ruff	2024-10-08 11:42:10 -06:00
test_verilog_gen.yaml	uart: fix #36, explicitly handle scientific notation in YAML config	2025-04-06 18:28:29 -06:00