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manta/examples/verilog/nexys4_ddr/uart_host_to_fpga_mem
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Fischer Moseley b31a655d58 tests: include building examples in test suite 2024-10-08 11:42:10 -06:00
..
.gitignore rename Nexys A7 to Nexys 4 DDR 2024-05-12 10:35:18 -07:00
build.sh tests: include building examples in test suite 2024-10-08 11:42:10 -06:00
build.tcl rename Nexys A7 to Nexys 4 DDR 2024-05-12 10:35:18 -07:00
manta.yaml rename Nexys A7 to Nexys 4 DDR 2024-05-12 10:35:18 -07:00
top_level.sv rename Nexys A7 to Nexys 4 DDR 2024-05-12 10:35:18 -07:00
top_level.xdc rename Nexys A7 to Nexys 4 DDR 2024-05-12 10:35:18 -07:00
write.py manta: fix code generation from config file, update tests 2024-10-08 11:42:10 -06:00