13 lines
1.2 KiB
Markdown
13 lines
1.2 KiB
Markdown
## What Goes Where?
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- `src/manta/` contains the Python and Verilog source needed to generate and run the cores.
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- `test/` contains testbenchs for HDL. Manta is written in Verilog 2001, but the testbenches are written in SystemVerilog 2012. These are simulated using Icarus Verilog, which produces `.vcd` files, viewable your favorite waveform viewer, like GTKWave.
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- `doc/` contains the documentation you're reading right now! It's built into a nice static site by Material for MkDocs, which automatically rebuilds the site on every commit to `main`. This is done with a GitHub Action configured in `.github/`
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- `examples/` is exactly what it sounds like. It contains examples for both the Digilent Nexys 4 DDR/Nexys A7 with thier onboard Series-7, as well as the Icestick with its onboard iCE40.
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- `.github/` also contains some GitHub Actions configuration for automatically running the SystemVerilog testbenches and building the examples, in addition to automatically rebuilding the site.
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## Tools Used
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- Verilator is used for linting
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- Wavedrom for waveform diagrams, and draw.io for block diagrams
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- GNU make for making it more convenient to run simulations.
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- GitHub Pages serves the documentation site. |