136 lines
3.4 KiB
Makefile
136 lines
3.4 KiB
Makefile
build:
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python3 -m build
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pypi_upload: build
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python3 -m twine upload --repository testpypi dist/*
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lint:
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python3 -m black src/manta/__init__.py
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python3 -m black src/manta/__main__.py
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serve_docs:
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mkdocs serve
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total_loc:
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find . -type f \( -iname \*.sv -o -iname \*.v -o -iname \*.py -o -iname \*.yaml -o -iname \*.yml -o -iname \*.md \) | sed 's/.*/"&"/' | xargs wc -l
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real_loc:
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find src test -type f \( -iname \*.sv -o -iname \*.v -o -iname \*.py -o -iname \*.yaml -o -iname \*.md \) | sed 's/.*/"&"/' | xargs wc -l
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test: auto_gen functional_sim
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clean:
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rm -f *.out *.vcd
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rm -rf dist/
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rm -rf src/mantaray.egg-info
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# API Generation Tests
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auto_gen:
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python3 test/auto_gen/run_tests.py
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# Functional Simulation
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functional_sim: io_core_tb logic_analyzer_tb bit_fifo_tb bridge_rx_tb bridge_tx_tb lut_ram_tb
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block_memory_tb:
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cd test/functional_sim/block_memory_tb/ && python3 foo.py
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iverilog -g2012 -o sim.out -y src/manta \
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test/functional_sim/block_memory_tb/block_memory_tb.sv \
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test/functional_sim/block_memory_tb/block_memory.v
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vvp sim.out
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rm sim.out
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io_core_tb:
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iverilog -g2012 -o sim.out -y src/manta \
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test/functional_sim/io_core_tb/io_core_tb.sv \
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test/functional_sim/io_core_tb/io_core.v
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vvp sim.out
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rm sim.out
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logic_analyzer_tb:
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iverilog -g2012 -o sim.out -y src/manta \
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test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv \
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test/functional_sim/logic_analyzer_tb/logic_analyzer.v \
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test/functional_sim/logic_analyzer_tb/sample_mem.v \
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test/functional_sim/logic_analyzer_tb/trigger_block.v
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vvp sim.out
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rm sim.out
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bit_fifo_tb:
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iverilog -g2012 -o sim.out -y src/manta \
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test/functional_sim/bit_fifo_tb/bit_fifo_tb.sv \
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test/functional_sim/bit_fifo_tb/bit_fifo.v
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vvp sim.out
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rm sim.out
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bridge_rx_tb:
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iverilog -g2012 -o sim.out -y src/manta test/functional_sim/bridge_rx_tb.sv
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vvp sim.out
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rm sim.out
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bridge_tx_tb:
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iverilog -g2012 -o sim.out -y src/manta test/functional_sim/bridge_tx_tb.sv
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vvp sim.out
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rm sim.out
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lut_ram_tb:
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iverilog -g2012 -o sim.out -y src/manta test/functional_sim/lut_ram_tb.sv
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vvp sim.out
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rm sim.out
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# Build Examples
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examples: icestick nexys_a7
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nexys_a7: nexys_a7_video_sprite nexys_a7_io_core nexys_a7_logic_analyzer nexys_a7_lut_ram
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nexys_a7_video_sprite:
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cd examples/nexys_a7/video_sprite; \
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manta gen manta.yaml src/manta.v; \
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mkdir -p obj/; \
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python3 lab-bc.py
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nexys_a7_io_core:
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cd examples/nexys_a7/io_core/; \
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manta gen manta.yaml src/manta.v; \
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mkdir -p obj/; \
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python3 lab-bc.py
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nexys_a7_logic_analyzer:
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cd examples/nexys_a7/logic_analyzer/; \
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manta gen manta.yaml src/manta.v; \
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mkdir -p obj/; \
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python3 lab-bc.py
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nexys_a7_lut_ram:
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cd examples/nexys_a7/lut_ram/; \
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manta gen manta.yaml src/manta.v; \
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mkdir -p obj/; \
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python3 lab-bc.py
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icestick: icestick_io_core icestick_lut_ram
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icestick_io_core:
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cd examples/icestick/io_core/; \
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manta gen manta.yaml manta.v; \
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./build.sh
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icestick_lut_ram:
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cd examples/icestick/lut_ram/; \
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manta gen manta.yaml manta.v; \
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./build.sh
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clean_examples:
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rm -f examples/nexys_a7/io_core/obj/*
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rm -f examples/nexys_a7/io_core/src/manta.v
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rm -f examples/nexys_a7/logic_analyzer/obj/*
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rm -f examples/nexys_a7/logic_analyzer/src/manta.v
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rm -f examples/nexys_a7/lut_ram/obj/*
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rm -f examples/nexys_a7/lut_ram/src/manta.v
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rm -f examples/icestick/io_core/*.bin
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rm -f examples/icestick/io_core/manta.v
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rm -f examples/icestick/lut_ram/*.bin
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rm -f examples/icestick/lut_ram/manta.v
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