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manta/examples/verilog
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Fischer Moseley 9f2dffb069 examples: make verilog/amaranth versions of uart_logic_analyzer match 2024-10-08 11:42:10 -06:00
..
icestick examples: make verilog/amaranth versions of uart_logic_analyzer match 2024-10-08 11:42:10 -06:00
nexys4_ddr meta: sort imports with ruff 2024-10-08 11:42:10 -06:00